I've wanted to hold off on posting on any progress of the board layout until I felt I'd mastered at least the basics of KiCAD.

What you see in the pic is an expanded version of the original PVB project. The 6 layer board size is 4.5"Hx3.75"V with a 120-pin main connector.

I've felt it necessary to post now because as one can see, only 2 signal layers are utilized for such high speed Random Access power! I'll have to use another layer dedicated for signals for the 120-pin interconnect.
So far I have the 6 layers setup like so: FRONT/GND/SIG/VCC/VDD/BACK. VCC is 3.3V. VDD is 1.2V. FRONT/SIG/BACK are signal layers. I've yet to route on the SIG layer.

There's a Xilinx XC6SLX150-676 at the center. 4 GSITech NBT SyncRAMs surround it with all signals routed on the top layer, except for the 4 individual clock signals. The pads can support the 400MHz 2Mx18 or the 300MHz 4Mx18 NBT devices. For experimentation purposes, the FPGA also has control over whether each SyncRAM is in Flow-Thru mode or Pass-Thru mode. The individual ADV pins are also under FPGA control to aid address loading in either these modes.

2 24-bit VideoDACs in the form of 48-pin QFPs, bottom mounted, have the potential to be present as well. The VideoDAC mounted closest to the 120-pin connector is the main video out. It will utilize the bottom DBA-15 VGA connector. The second VideoDAC was wired in to aid in development if necessary. There's the potential for quad-buffering as well, so I added in the 2nd VGA connector.

The purpose of the 120-pin main connector is to route 24-bit RGB data out from the board on the top row of pins with associated HSYNC/VSYNC/PixelCLK while also accepting 24-bit RGB and associated signals on the bottom row of pins.
The middle row has I/O signals to allow for board control. It is 16-bit wide I/O data bus and 9-bit wide address bus allowing for a potential 512 video registers to be programmed on the fly from an external controller board.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Watch out for the rules on SSOs - simultaneous switching outputs. See p36 of http://www.xilinx.com/support/documenta ... /ds162.pdf
Similarly be sure you've got enough decoupling caps on the power rails. See p13 of
http://www.xilinx.com/support/documenta ... /ug393.pdf

(I mention this because of some teething problems seen on the multicoprocessor board over on stardot.)

That's a long thread over there and so I tried to gather which board has the 'suspected' SSO issue. Is it the GODIL you had donated?



Also, I suspect the 1 thing which I've noticed is a real life effect of main frequency vs. noise & presence of bypass caps when you compare WW to a 4-layer board.

I for one like to toy with a lack of bypass capacitors as regards to a spec sheet. As a hobbyist and tinkerer, this is a habit I've grown with ever transitioning from using wire-wrap to 4 layer boards. I like to experiment, I'm not an engineer.
Keep in mind, when I was utilizing WW in my projects main volts was 5v and frequencies around 20MHz with discrete logic. I was religious using bypass cap's and manually soldering in copper wire for the power/GND rails on all IC's. My failures and measurements dictated that I do this for the circuit to work. BTW breadboard sucks!

When I transitioned to 4 layer boards, main volts was 3.3v and frequencies I used jumped to 100MHz+ with FPGA's. I was pushing Arlet's 6502 core and I had noticed that bypass cap's were not as critical as the hardware seemed functional...

What really was interesting in my latest failure of PVBV2 is that I noticed 1 thing: When I switched from an external 3.3v 100MHz can oscillator to a 3.3v 200Mhz can oscillator, the 1080p picture was slightly improved.

IMO this says one thing: There is a natural bypass capacitance of the powers/GND plane VIAs especially in regards to the 256-pin BGA power/GND vias under the chip and the higher speeds started to take advantage of this fact.

Maybe Garth will expound. Looking forward to it!

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

My understanding here is that the ground and power planes are typically the middle two layers on a four-layer board, and that they count as the two sides of a capacitor with the board material itself as the dielectric... But I don't know how much capacitance this gives, or how it impacts the usual bypass and decoupling capactiors used with digital logic.

Sorry, yes it is a long thread. No, the GODIL was fine, but has only an 8-bit wide RAM, and is more costly than a purpose-made design, so Jason Flynn designed just that, with two RAMs and therefore a 32-bit wide memory path. Here are some relevant photo posts:

Early board layout and schematic: http://stardot.org.uk/forums/viewtopic. ... 780#p98780

Later layout and photos: http://stardot.org.uk/forums/viewtopic. ... 901#p99901

Front and back: http://stardot.org.uk/forums/viewtopic. ... 21#p103121
(The co-pro is the red board. The Beeb is still a popular micro and there's a whole variety of addin boards to be compatible with - both mechanically and electrically.)

First round of decoupling: http://stardot.org.uk/forums/viewtopic. ... 54#p102654

Second round of decoupling, on a silver prototype board: http://stardot.org.uk/forums/viewtopic. ... 35#p106935
And again: http://stardot.org.uk/forums/viewtopic. ... 73#p106773

This was a complex and ambitious project: two RAMs, both sides of the board used, two-layer board, 4 different CPU architectures, a number of HDL bugs in both CPUs and peripherals, some firmware bugs, at least two different busses to hook up to. It's a great success, now that all of that is ironed out. (I think it's all ironed out now...)

One interesting point is that two people were making good progress with a prototype (maybe even two rounds of prototype), and then when a dozen or more people got hold of their revised design, we started to see problems. The moral is that you do need some wide experience with beta testers if you're making something like this for a large audience. A one-off design for yourself only is of course easier.

Cheers
Ed

Ref: hoglet's gitub rep for this copro: https://github.com/hoglet67/CoPro6502

Other interesting posts from the thread:
BCD fixes: http://stardot.org.uk/forums/viewtopic. ... 86#p103386
Table of available CPUs and speeds: http://stardot.org.uk/forums/viewtopic. ... 17#p106217
A much faster Z80: http://stardot.org.uk/forums/viewtopic. ... 01#p106301
Traces of the bus interface: http://stardot.org.uk/forums/viewtopic. ... 31#p106731
Adjusting output drivers: http://stardot.org.uk/forums/viewtopic. ... 62#p106762

The dielectric constant of the common FR-4 PCB material is 4.1, and the capacitor equation for two parallel plates is C=0.2235*K*A/d, where C is in pF, K is the dielectric constant (4.1 in this case), and A is the area of the plates in square inches. So if the layers were evenly distributed in a .062"-thick board, the dielectric thickness between the two inner layers would be about .020", so you'd get about 45pF per square inch, if I did it right. That's not much, but read on.

Ideally, you have every signal layer next to a ground or virtual ground plane, with no other layers between them. (A "virtual" ground plane can be a power plane that is bypassed to ground in all the many right places.) For four layers, having power and ground planes together in the middle of the board is fine, but if you went to six layers, you're better off putting two signal layers on the outsides, and two more between the power and ground planes, with traces running mostly at right angles to the neighboring layer. There is a board technology that puts power and ground layers just a couple of mills apart so as to increase the capacitance between them, but as I understand it, two parallel planes have no inductance anyway, as long as you stay away from the edges, so you no longer need a bypass capacitors at every IC. I believe hi-speed digital-design guru Dr. Howard Johnson said this, and it makes sense, but I have not been able to find it again.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Hello, just a quick update on everything....

I'll be returning to make further progress on this project probably in a few months. I haven't given up by any means, in fact the board layout was almost done.

I just needed to see concrete successful results in at least one of my hobbies, so I'd decided to concentrate on my "race car" for awhile. Currently enjoying upgrading the stock rear axle of my old 1986 IROC Z-28 with a posi unit from a 2002 Camaro SLP SS and more stuff. Wrong forum, I know! Anyway cheers, fellow 6502/65816 enthusiasts. Going back to lurking until late fall. See ya!

EDIT: Here is the forum where I posted info and pics of my '86 IROC mod's.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Good to hear from you - was beginning to wonder why you'd gone quiet. Enjoy the summer!

Almost time to finish the layout! I've backed the original work up and am ready to start considering what needs to be done next to start utilizing the last 'SIGNAL' layer in order to route the incoming RGBin signals to the FPGA from the bottom row of pins on the 120-pin main connector.

This part will take some consideration because although the HSYNC/VSYNC signals have been routed on the top/bottom layers for both videoDACs, the 3 RGB signals still need to be routed from the videoDACs to the VGA connectors and it cannot be done on those layers. Routing these few signals will most likely have to be done on the 'SIGNAL' layer and will cut across half of the connector. This will force me to route all RGBin traces around the left of the bottom videoDAC. Gonna be tight, but I think it's doable. I'll work on it soon.

EDIT: Also, I'm feeling more confident about using KiCad with the Eurocircuit fab house. KiCad generates the RS-274X gerber files and drill files necessary. For a single run of a 6-layer 4.5"x3.75" board, it's gonna be a $185 gamble but I'm ready to jump in to a new fab house.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Another update:
I became discouraged when I lost my progress due to SSD failure of my computer dedicated to Xilinx FPGA work on this project. Sounds pathetic I know. So I'll stop there with my computer problems that happened over a year ago. Today I got in a couple new 7200RPM 1TB HDD's and ALSO my engine project is leading me towards 68HC11 research and possibly back into this video project. We'll see how far behind the data loss a year ago puts me... I can guarantee it won't put me behind Express PCB 4 layer, but that is far behind for what I wanted to do for video with 4 large SyncRAMs and a large FPGA controlling all data/address paths. I may have to make a sacrfice...

Anyway, physically, the engine is almost complete at this point, only needing the high performance cylinder heads which are a great sum of $$. I aim to go into the cpu of the Engine Controller Module and modify the code and also tables. A few smart people over at thirdgen.org have already done this. I aim to conquer quickly this electronics part of my engine project...

Aim high, as they say. Reconciliation is close.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Friendly recommendation: force-air cool those disks. As the temperature of a running drive elevates, the interior air density decreases, causing the flying gap between the heads and platter(s) to close up. This sequence of events makes the drive more susceptible to a head crash. Also, a drive that is running hot will have to more frequently recalibrate, which will affect performance.

Maximum drive life will be achieved with good cooling and by minimizing the number of start/stop cycles.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Thanks for your input BDD.

The SSD's were the greatest disappointment. They lasted maybe 2 years.. And the warranty program was terrible. Got replacement units that lasted maybe 2 months..

I'm regressing to more reliable HDD's, 7200 RPM 1TB @$50 ea. Also looking into RAID arrays... Ive experimented with RAID 0/1 before but I would like Parity correction in hardware RAID on the motherboard. I have such a MB, but I need to slowly get back into this...

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

We continue to build our servers with mechanical disks, as SS disks have not lived up to their hype. It appears at this time that the best mechanical SCSI disks will outlive the SS disks.


RAID 0/1 is false security and tends to demonstrate lackluster performance. If you want to go the RAID route you need to consider RAID 5, which can be done with SATA disks, but is better done with SCSI (SAS) disks on a host adapter that provides embedded RAID 5 hardware support. As a general rule, SCSI disks tend to be more trustworthy and longer lived than SATA disks. The latter are considered consumer products and are designed to be inexpensive, with a typical life-expectancy in continuous service of around five years. SCSI disks are designed to be reliable in non-stop service, and often last 50 percent longer than the same size disk in SATA. As always, you never get more than your money's worth.

You should also implement a trustworthy backup regimen. RDX cartridges are good for that purpose if you are on a budget. LTO tape is much better, and once you get past the cost of the drive, it's relatively economical to implement multi-way redundancy. My office server is backed up on LTO-3 cartridges, a total of 14, seven for odd-numbered weeks and seven for even-numbered weeks. My shop server, on which I do all software development, is backed up on LTO-2 cartridges, seven total. LTO tapes typically achieve a transfer rate of around 40-60 GB per hour.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

The motherboard I use (Asus P7P55D-E Pro) is RAID 5 capable. A couple more weeks and I plan to get a couple more 1TB SATA6 HDD's to create a RAID5 array. It's okay if ONE HDD fails every 5 years... I guess I need to cross my fingers that 2 don't fail at the same time. lol.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Hello 6502.org!
I've completed a new desktop build around the 6-core Intel I7-6850K with a RAID 5 array with 3x 1GB drives for the server/backup a few months ago.

Also, I've reconsidered using KiCad. I've gotten pretty far using ExpressPCB and couldn't afford to throw money with a new process and I've been keeping track of ExpressPCB PLUS software updates. Today I got my feet wet with the current version 1.14 trying to put soldermask on top of a via and it seemed to be a success. This was the small detail that killed my PVB project as I had moved on to BGA IC's and the via rings under the BGA were exposed thereby shorting to the BGA pads during mounting.

So the project is going to change a little I think. Instead of pursuing parallel video boards, I would like to do 1 board with a header to control it. And try to move up to 4K resolution. Not sure why they went from 1080p vertical spec to 4K horizontal spec, but I guess that's progress. I see Intel is running 4K video out of their CPUs at around 330MHz IIRC, and I was running the PVB project at 300MHz, with all needed clocks divided down from it.

Plans are to use the same layout as the pic above using the same BGA 676pin Xilinx Spartan 6 and some larger syncRAM's. Will have to see what's EOL. So much EOL these days on some of this stuff.

Best Regards.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502