I recently posted a
note on the progression of speeds of various 6502 implementations, telling a story which runs from the 1MHz original NMOS chips to today's FPGA cores which promise 100MHz operation.
I got myself a bit confused in the process, and realise that the topic of the fastest FPGA cores needs a bit more space and some more facts.
As far as I'm aware, we have two cores which promise speeds over say 50MHz. That is,
Arlet's core (and the
65Org16 derivatives) and
Michael's core (a 65C02 workalike.) If anyone knows of additional cores running over 50MHz, please let me know and I'll edit this head post.
There are two immediate caveats: firstly, that the different FPGA chips have different intrinsic speed. We've seen that a Spartan 6 might reach speeds about double that of a Spartan 3, for example. Secondly, that single-cycle memory access is limited to on-chip memory, and the cheapest and non-BGA FPGAs don't usually have as much as 64kbytes of block RAM - so off-chip memory is likely to be necessary for many projects.
I don't think we've yet seen a cache on FPGA, so those designs which use off-chip RAM are probably going to hit multi-cycle access times for all RAM access. In principle we can easily use on-chip RAM for zero-page and stack, but I don't think anyone here has yet done that in a design which has off-chip RAM too. (Please correct me if I'm wrong) [But note, Michael does report that additional multiplexing and decode for mixed on and off chip RAM cost a little speed - so something has been tried.]
As I understand it, Michael's core originally had a target clock speed of 100MHz (and offers some cycle-count reductions.) But notably, the core runs at this speed only when using distributed RAM - usually there's less of that than the block RAM, for which the core needs to run with a wait state, effectively halving the performance. However, all the builds and timing analysis reported for this core are for the Spartan 3 (the higher speed grade, -5) - we could expect greater things from Spartan 6. The github repo presently focusses on the problem of an FPGA using external memory, not on the fastest core in a self-contained system, and is still a work in progress. More recent releases seem to be slower implementations than the earlier ones - I think the latest reports are showing a core runs at 64MHz with a 4-cycle memory access making it an effective 16MHz, allowing the use of relatively slow external memory. I'm not aware of any reports on the forum of this core running at speed or in a system - will update if any come to light.
On the other hand, Arlet's core, at least in the 65Org16 flavour, is reported as running at 100MHz - on Spartan 6 I believe - and has been connected to fast 6ns (167MHz) external SDRAM. (Does that mean single-cycle access?) I'd welcome clarification from Arlet or EEye on what's been seen on boards: there have been impressively long threads but it's difficult to distill it to a performance summary. I think I'm right in saying that there are two board designs?
(For my own part, I've reported 50MHz with an Arlet-type core, on Spartan 3. I have a Spartan 6 board but haven't made use of it yet)
I'll update this post as information comes to light, so it can serve as a reference.
Code:
Core: Clock: FPGA type: Memory access: Memory type/speed: Relevant threads or posts:
Arlet 45MHz Spartan 3 ?? SRAM http://forum.6502.org/viewtopic.php?f=10&t=2644
M65C02 74MHz Spartan 3A (-4) 4 cycles Async SRAM http://forum.6502.org/viewtopic.php?t=2163&start=132
bc6502 117MHz Spartan 6 (-3) ?? ?? http://forum.6502.org/viewtopic.php?t=2500&start=42