Hi EE
I had a look at the
userguide for the LX9 microboard which I linked in
this post, where on page 9 it says
Quote:
It is highly recommended that anyone creating a Spartan-6 MCB design thoroughly read the two User Guides (UG388 and
UG416), the MIG Master Answer Record 33566, and the associated Answer Records linked from that Master Record
MCB is the Memory Control Block, the free builtin SDRAM controller on some spartan6 devices. Unfortunately, the table on page 13 of
UG388 tells us that your chosen LX9 has no MCBs and also gives some insight into how complex an SDRAM controller is. So SDRAM is perhaps going to be extra difficult with your chosen FPGA.
I agree that a cache isn't necessary - a buffer would be sufficient - but the latency will hurt performance unless there's enough cache to keep a healthy hit rate. It
seems the effective speed of 167MHz SDRAM might be 14MHz or so for random access. I think SRAM will be the straightforward answer, although as Arlet says, you can help by mapping block RAM into important places.
(However, I don't think 4Gbyte is necessary to show off the advantages of 65Org16. Even with just 64k of memory, having the whole of memory available for zero page, for stack, and having reasonable size buffers accessible with single-word indexes are all advantages available at once. Anyone concerned about stack overflowing into data areas need only fit 256k of memory to have 64k of dedicated stack. [or make a variant CPU with a smaller stack pointer.])
1 Mbit SRAM is 64kwords x 16 - is that the size you have in mind? (I recommend you spell out Mbit and Mbyte to avoid confusion!)
Cheers
Ed