If you really want that kind of quality, remember you'll have to keep the sampling jitter down in the picoseconds--yes, picoseconds--to have noise products at least 10 bits below the program material when there's 20kHz content. There's a note about that on my circuit potpourri page. 10 bits with a 44ksps sampling rate and adequately low jitter can give much better quality than the best cassettes could.


If there are enough unused ones on a given board to matter, you could omit the holes for those pins and snip those pins off on the PCB end before inserting the connector and soldering it. That 96-pin DIN connector is sure nice though.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Here is the link to the SSM2604 data sheet, I should've provided it before. It's a 20-pin QFN, everything is serial.

I have to make a state machine in Verilog to create the 16-bit parallel data. Since the 2 serial lines that involve recording, already go to the FPGA from the SSM2604, I have a chance to analyze the data once I get the state machines correct.
What I really wanted to do was to have the capability to output the parallel data along with the clock to an offboard DAC as proof, something I could hear.
Currently, all this K1 controller board can potentially do with this serial data is display it in the graphics, no other output unless I add this connector I mentioned.

EDIT: Then I have another idea for this connector. Since this is a 16-bit parallel interface, I'm looking into the signals necessary for (old school) parallel ATA. This is the beauty of FPGA.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Instead of placing the PATA/16-bit audio connector to the NE, it makes sense to place it to the NW (underneath the reset tactile switches) so the mini-HDMI, stereo I/O, and RF sections can rise to the top of the board where their connectors should be. Also, the RF section will have more freedom to expand.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I've rethought this 16-bit I/O interface and decided against it at this time. I already have on-board storage overkill with 1Gx16 SPI FLASH and a micro-SD FLASH adapter. Also, there's no easy way to route more pins out through the XC6SLX25 on a 4-layer board. I probably could...

What I have been focusing on, are the challenges that await me mounting a 676-pin 1-mm BGA IC. I've re-read through one of my favorite threads here on 6502.org: the BGA mount thread. 1 expert suggests stencils and solder paste and reflow oven. Another expert suggests a hotplate and flux.
For me stencils are out of the picture, so is purchasing a re-flow oven. Too much money.
I would like to have 4 more holes drilled into the hotplate I currently own and add 4 additional heater elements in series/parallel combination to the 4 that already exist. Then when mounting the 676-pin BGA, in addition to the hotplate for the heat below, use the hot air from my SMT reflow station for hot air from above.

I post here tonight because I'm excited about a new purchase, rather cheap, but looks extremely useful!
It was brought up on the BGA mount thread. Looks like it(Adafruit 220x 5MP USB camera) has been updated to 5MP camera, still with 220x magnification!

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

What about one of the toaster-oven reflow controller kits? The impression that I get is that the reflow controller kit plus a brand new toaster oven together would probably cost less than your new boards.

Hi nyef,
I meant a professional re-flow oven. It's $200US+ mentioned in the BGA mount thread I posted above...

enso had tried to use a toaster oven with a PID controller, but he had complaints of vibrations from the custom installed fans.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I've done a 4-page writeup on the intended functions of this board. It's very general, but does give some insight of my expectations of the inner workings. Should be visible on MS Wordpad. I will post the final version of this writeup on the head post.

Very close to a final PCB layout.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Link to read that doc online:
https://drive.google.com/viewerng/viewe ... ?id%3D2042

I have a Proctor-Silex toaster-oven here that I got at a garage sale for five bucks. It has a fan in it but runs vibration-free.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Just stumbled upon this site, very impressive work!

This sounds like a really fun board, Are you planning on using an external programmer to download the bit image into the FPGA or are you going to use a SPI Flash programmer? If you plan to go with the SPI Flash programmer have you looked into FTDI's FT2232H, or the bigger sister FT4232H they offer a wider variety of communication methods between a host computer and an FPGA. For example on my smallest FPGA devboard http://wiki.cospandesign.com/index.php?title=Dionysus I use the FT2232H to both program and communicate with the board. It also allows me to communicate with the board at a rate of about 25MB/s. If you are interested I even have some HDL (Verilog) and Python scripts that facilitate communication between the host and FPGA.

This is great because you can stream video to/from the FPGA (albeit at a little slower rate at higher definition) but you can verify the video output/input pipeline even if the other video input/output functionality is not working. Here's an example of project I did that accomplished video output with an LCD: https://www.youtube.com/watch?v=QLlUxiCfyig. I need to make a video of using my small camera board but regardless video input is also possible with that chip.

Is it possible to share a block diagram of your project? I'd like to see it at a high level. I use this tool http://www.yworks.com/en/products_yed_download.html to create block diagrams of my projects to share with clients, in my opinion it creates very professional looking block diagrams that really help people get the high level idea of my designs.

I look forward to seeing how everything turns out.

Dave

Dave thanks for the heads up on FTDI's FT2232H/FT4232H, and I would be interested in your drivers. I probably won't need them for awhile though. I'll PM you my email...
I was originally planning on sending data in RGB bitmap form, for simple bitmaps or sprites, through a FTDI230X. I had used a similar product in another project, although different manufacturer, the MCP2200 USB to UART. I was able to reliably transfer data files using the br@y terminal from the PC to project @ 1Mbps. This IC you mention may add alot. I will investigate!

In this part of the project for the K1 Board, I am taking a different angle than you, by using an HDMI receiver for the HD video streaming. I really just wanted to be able to connect my 14MP camera with 24X optical zoom & its mini-HDMI output to K1 and see it work on my system...

I am still doing a final writeup for this board, but there will be block diagrams included for this board as well the entire system interconnect.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Also, thanks for the pointer on the yEd block diagram tool.
I've put it to use to make the block diagram below for the total system inter-connect. Very nice tool!
Today, I also made a parts list for K1. I'll add it soon.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I finished my simple little MS Excel parts spreadsheet to auto add/multiply for parts prices (prices x QTY) then add the $ext column for the total...
It's not pretty, I thought there was an error in the addition or something. I mean $514?! I can't afford that for a prototype board. On top of the $320 manufacturing cost for 2 stinking boards. This is close to insanity, IF I were to populate the entire board at once, which would be very foolish... Maximizing a board potential is not so foolish when one is paying for real estate.

If the audio section, RF transceiver section, touchscreen controller sections were left unpopulated, parts cost would be down to $280. This might be manageable... but still $318 board + $280 parts is such a risk for me since I am a novice at BGA mounting. I'm very tempted to start smaller, and design a new PVB around 2 SyncRAMs and a XC6SLX25 1mm 256-pin BGA. I've already started a new thread about this.
I have the SyncRAMs I could salvage from 2 boards, and I have an XC6SLX25 256-pin BGA I bought just so I could see the solderballs. All it would take is a new design and around ~$200 for the boards. This is in the ballpark.

One of the glaring costs is the SPI FLASH I chose. Sh*t, I might as as well look into interfacing to an older SSD, but this requires SATA.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

EEyE:

I haven't tried to use the SPI Flash that you selected in one of the multiple IO configurations. However, it is possible to use them in a 2x and 4x mode. I suspect that you could implement a very fast, two bank interface with between one and four of theses devices. You can use the decoder to allow you future access to the other devices on your board after testing your board with one to four devices. That reduction in parts count alone, coupled with a change to a smaller pin-compatible FPGA will provide significant savings.

My recommendation was for you to use the SOL16 package for all of your SPI Flash. The configuration memory device and any user memory devices. To reach the 1Gb density level for your configuration device, you'd need to provide the two chip selects as you're doing for your SPI Flash array. However, I don't think that will be advantageous. At some configuration device density point you'd loose support in the Xilinx tools for the in-system programming of those devices with the Xilinx indirect programmer. However, you'd be able to populate all of your Flash slots with a single inexpensive device type such as you are using for the configuration memory. It also supports the multi-bit interface. Thus, you'd be able to test most of your IP without having to expend big bucks for the prototype, and after that is successful, you can spring for the higher density parts.

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Michael A.

Hi Michael,
I wasn't planning on using Xilinx ISE to program the 1Gx16 SPI FLASH array...
I see now where misunderstanding may have occurred and apologize for the confusion. I forgot to include the 32Mbit SPI FLASH (U8) which is dedicated for the FPGA programming through JTAG, I'll update it soon. The XC6SlX45 676-pin device only needs 16Mbit, but I thought it might be nice to experiment with multi-boot, although I've read in Xilinx forums that they've had issues with multi-boot. Multi-boot is not critical in this case, but nice to maybe experiement with the issues...
The 16Gbx16 FLASH ARRAY is on a separate SPI bus. I will update the 'comments' section of the parts list with the appropriate IC# on the board layout.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502