Summary: I present the design and implementation details for what may be the most inexpensive and minimal FPGA board. The board is capable of hosting Arlet's core with 8K of RAM/ROM running at 100MHz, glue logic and custom IO. I will update this top page with the most current information as needed.

Features
-Fast Xilinx XC3S50 FPGA (grade 5), 768 slices, 8K BRAM
-60MHz oscillator (other frequencies can be derived easily)
-Onboard power regulators (1.2V and 2.5V)
-Xilinx Platform Flash
-Native JTAG connection to both FPGA and Platform Flash
-60 IO pins connected (2 are limited: oscillator input and LED output)
-3.3V operation, 5V tolerant (according to information available, not tested)
-IO pin layout allows breadboarding, PCB or wire wrapping
Possible uses
-Stand-alone 6502 controller (like arduino but with a 100MHz 6502!)
-A controller with up to 4 PicoBlaze processors
-Glue logic for 6502 (or any) project
-Custom circuitry and interface (keyboard, mouse, VGA, SD card, etc)
-Anything you can imagine
Motivation
Every now and then I wish I had a truly inexpensive FPGA-based controller with a few dozen IO pins. The devboards out there are generally over $100. Devboards stop being available as soon as a new FPGA generation comes out.
Devboards are generally not minimal, and are often built to showcase some or other technology. I could not find a truly minimal board. Boards like Xula have no native JTAG, not minimal (due to the PIC chip) and require yet another set of tools to configure.
Development status
Aug 18 2013 - The board is in its 5th revision (E) and is stable and as far as I know is bug-free.
Availability
Small quantities of assembled boards are available on experimental basis to 6502.org members for US$20 plus shipping (for now).
PM me if you are interested in assembled boards, parts or bare PCBs.
Working with DILDAR
The board is a plain-vanilla FPGA with a JTAG interface, so there is nothing special about using it. Any circuit that fits the XC3S50 should work.
Intellectual Property
Unless otherwise noted, all information presented here is placed into the Public Domain where it is legally acceptable. I don't care much for the IP situation; the design is a straightforward and commonsense implementation of publicly available information, and I do not believe that anyone (myself included) could have any IP claims. Any designs, software or physical hardware you may get from me should be considered experimental, as is, and not used for any important purpose.

I've also created a version of this board with a 128K SRAM chip. http://forum.6502.org/viewtopic.php?f=10&t=2644

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

Top view of the layout (rev E):

On the upper left, crystal oscillator with a shorting block to disable it (in case you are using an external clock and need the IO pin). The LED is on the lower left (marked 'l'); the FPGA pin is available here as well. Decoupling caps are small (0603) pads, power caps are larger (0805) pads. There are also two resistors, 330 Ohm for the LED and a 120 Ohm for the power supply. Also visible are pads for the FPGA and the Platform Flash.

On the right side there are two connectors: a 6-pin JTAG and 3.3V/GND inputs.

Bottom view:

The only parts on the bottom are the two voltage regulators for 2.5V and 1.2V required for the FPGA operation. There is also a handy chart of the pin assignments. The bottom rows of the legend are aligned with the pins (one pair is above on the right since the power connector is blocking the spot where it would go). The top legend has lines to clearly indicate which row belongs to what pins.

_________________
In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut