I wonder if someone would be interested in making a glue chip to emulate some
banking and decoding circuitry with some latches and etc. inside?
I would need to make the schematic of the circuit I believe.
Thanks Cy

Check out one Daryl already offers, at http://sbc.rictor.org/decoder.html . He apparently will do custom ones too.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

While it's an overkill, I've been contemplating using an XC3S50 for that purpose. I have a bunch of them, and the total cost of a '50 and and an XCF01 is very low, providing 63 IO pins. There is lots of room to implement other IO functionality - IO decoding, UARTs, SPI, and even USB (god help us all).

While not directly 5V compatible, it seems that you can drive 5V circuits with a resistor (300?).

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

I took to long to reply and lost all I typed in so here is the diagrams without the descriptions etc

Well I'll try again,
The dual drawing is the original glue chip with maybe a little more than needed inside.
It was made to be used in several types of modules controling RAM /ROM memory, I/O,
memory and I/O paging, module type identification , power supply switching the method of
battery saving used before CMOS could be used for these chips.
The strange power system does make it somewhat more complicated than need be otherwise.
The original chip was used in several module types and was selectable to different function by
3 select pins that would change or add function to different input and output pins.
I have little documentation on these but was able to get some from device manuals.
Most of which is added into the drawing showing alternate functions known.
There were some other uses I have no manuals for that would need to be hand drawn from reverse
drawn schematics etc. Some information also can be extrapolated from modules not implementing these ICs.

The other messy hand drawn diagram is what I thought would be a minimal replacement to be used
to bank in a large memory chip taken from a different memory module and also eliminating address and data buffers that may not be needed using the larger memory IC,s. It was drawn a few years ago and is quite messy as you can see.
There would likely need to be a latch added to store and output the selected bank into the high order address
pins or decoder ic. This was for the Panasonic HHC line of computers.
Also there are several module addresses used and bank addresses within each module with possible 128k
ram or rom per module address but a module can use more than one module address as in the large multi ROM
modules. THese modules do make it dificult to use more than one other module in addition because of the
expansion port that does not allow the multi module expandr to fit into it and possible other conflicts.
These computers do allow a maximum bank size of 16 k per rom or ram bank and only 8 k of ram in the
internal installed ram area, that most units contain 4k ram that can be easily extended to the 8 k max using
2 more 6116 chips piggyback on top of the originals and one pin each bent up and wired to the extra unused
outputs of the decoder driving the original 6116s.
in the messy looking drawing there are a few places with arrows that lead to other sections on the page to prevent some of the criss crossing of lines.
There is most of what I typed in yesterday and lost when I was rerouted to sign in again when posting.
This time I will select and copy it before trying to post so I can paste it in if deleted.
Thank You for now,
Cy