I will leave the Sim up to you then! While it is interesting, it seems very in depth and very time consuming to learn. I would prefer to be an end-user.

I have the 48MHz clock, I can always divide it down... I just added the reset switch and rearranged the board. I made some space for at least a 100-pin QFP adapter, and some small expansion sockets. I realized too, I forgot about the LED driver for the display. Also, I soldered the XCF02S FPGA PROM, and the DS1085L oscillator. I always proceed slowly at this point... I will leave the original pic above alone. This one I will edit when the LED driver comes in. I will post 1 more pic if anything changes after that. BTW, the SDHC card is just for show.

EDIT: Moved the USB connector next to the 20-pin FFC connector.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I mean, if you want to simulate the 6502 core, you need to make a small testbench to generate a clock, otherwise the core isn't going to do anything. Here's a simple tutorial: http://www.cis.upenn.edu/~milom/cse372-Spring06/simulation/ And here's a snippet from that page showing how to make your own clock:


On the real hardware, you can divide or multiply the clock frequency easily by using the DCM (digital clock manager) module inside the FPGA. No need for external circuitry, and you can change the frequency by just changing some parameters. http://www.xilinx.com/support/documentation/application_notes/xapp462.pdf

I am failing to see the absolute need to do a simulation. Forgive me for being hard-headed. I realize that about the divider too...

The only other IC I was making space for was a 100-pin QFP adapter for a CY7C67300. Then I will be out of room. Just trying to think ahead here, I may not need it though I am planning for it. Xilinx has there own data sheet for this IC, even though it was meant to interface to a powerPC core. This tells me the Cypress USB controller is a unique piece of hardware necessary for USB control. It has IDE channels too (which is why I was making room for expansion sockets too), PWM's and more. I already have the IC, would have to buy the adapter. Adapters are killing my budget though, which is why I am holding off at this early stage.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

... must've double clicked sorry. *Post needs to be deleted*

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Hi ElEctric_EyE ,
Do you have some video clips showing you system in action , or this is only a concept ?

Sorry for being off-topic but ...


I don't know about Xilinx, but Altera has SignalTap II which allows you to do just that! It's quite nice, although it uses the on-chip ram to buffer values, so it can be difficult to use on a design that's already using all the internal RAM.

Hi bound. I sorta knew you'd be back in town after I mentioned USB.

I have a couple videos. The latest one shows my PWA project @3.3V running @20MHz using discrete componenets (i.e. W65C02, 2Mx8 SRAM, 512Kx8 Flash, etc.). Soon afterwards, I fit a PS2 core made by Daniel Quintero (contribution to opencores.org) into the Spartan 2 (XC2S15) in the same PWA project, but I needed an I2C core, which wouldn't fit. This was the point at which I realized fitting a wishbone core into a Xilinx FPGA was very easy.

Hence this dive into a multi-core FPGA... I am very confident, at this point, of fitting multiple cores, but we shall see if I am successful!
I have ~$250US invested on this board alone (50%+ is mostly SMT adapters). I think it will work, I would like to share with the 6502 fans! Yeah! Never give up!...

Realize though, 2 people proficient in Verilog (Arlet & Xor), have said USB is a difficult undertaking with the 6502 controlling...

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Xilinx has this feature too, but as far as I can tell, you need a paid license to use it.

I wasn't aware the DCM's were that powerful. I knew they had phase shift abilities, but I assumed, from the symbol information, that their "divide by" powers were limited to 2,4,8,16, etc. like any common counter. I'm going to print this out for further study, so I can read away from the computer while at work...

Been doing alot of printing recently on info regarding the Spartan 3. Actually the wife has done the printing. Turns out Xilinx has learned alot from their Virtex II technology and funneled it back down into the Spartan 3. Maybe soon we should compile a small list of these app notes pertinent to this family. Xilinx has excellent documentation that's for sure.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

ElEctric_EyE : I'm impressed. Nice project .

Thanks m8.

Back to the layout finalization. Got the LED driver in today. Secured it to the Vectorbord with 2 strips of magnetic wire. Same $10 LED driver (5VDCin-23VDCout from NHD) as used in the PWA...

Using the last pic as a reference, after moving the USB connector to directly under the 20-pin FFC connector on the upper right side, there is enough room to fit a 144-pin QFP adapter socket underneath the Spartan 3, with the right edges of the Spartan 3 in line with the 144-pin QFP adapter.
Not thinking of any IC, but this is the max... Also, directly under the Flash next to the Spartan 3, 3 40-pin connectors will fit side by side, with 1 more 30-pin connector fitting directly below the USB conector (as shown below)
_____________________________________________________________

A pic is worth 1000 words. Gone through about 100 words already, I figured I'd post a pic. This is the last one. It will be edited slightly in the future with labels and the addition of 3 40-pin connectors (trying to find wirewrap versions)... (The 144-pin QFP adapter will be used in the PWA project, just using it here as a temp spacer. I didn't even think it would've fit although I did have to edge the Spartan 3 and Flash 1 step closer to the VR's)

Edited: Soon

Underneath:


Edited: 1/26/2011. Added underneath per request.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

HI , ElEctric_EyE
Just have few questions for you
1) What is the 1.2v regulator in your system ?? (looks like they all in to-220 )
2) 2M x8 flash ( what for ?)
3) Sd card interface ( do you what to write a fat16 or fa32 drivers/software)
4) I can’t see any ram chips
All looks like a fake to me no offence
I’m new in Spartan 3 designs , do you need pull up resistors in ps2 interface ? ... and the last one , can you please send some pictures of the bottom side of your board ?

Hi bound. No offense taken, I appreciate your interest!...

This is a work in progress, and the beginnings you see here. Progress will be slow at times, for various reasons: I only have 2 days a week to commit, I alone do all the work (software & hardware), and I wirewrap.


They are MCP1826 series (identical, in pinout, to the old 78xx series) of 1A DC regulators. The one you point out is a 1.2V 1A in TO-220. The one thing that differentiates them from the 78xx series is their Vout to Vin is low ~2-3V IIRC. All the 78xx series had Vin's up to 35V? Guess this helps in controlling heat... I feed 5V into 3.3V, 3.3V into 2.5V, and 2.5V into 1.2V. Anyway, the 1.2V feeds the internal core which is very well filtered at this point, via the VCCINT pins.


Storing data after power has been removed. One that large can store 1 whole 640x480x3bytes screen full of info, and have another 1M for programs, icons, etc. Also makes it possible to do a "soft" reset (will have to add another reset switch)...


No drivers are planned at this point. It is meant as an easy data transfer system. The plan is to store raw binary data from the PC onto the SD card, specifically from MK's 6502 assembler, and then to transfer data to the 2Mx8 Flash, and finally into the core using commands from the keyboard.


The 6502core will see 64K, all of it internal BlockRAM running very fast. There will be an ability to transfer data to/from the FLASH at slower speeds, to accomodate the 70ns access times of the FLASH, to anywhere within the 64K BlockRAM, again using commands from the keyboard.
Right now I am reading up on how to use synchronous RAM, as all internal RAMs are fed by a clock.


So far, I've gotten away without using them. I've seen 4.7K pull-up resistors in most designs. May have to add them later...


I was thinking a bottom pic would be necessary too. I will work on it, expect it to be edited into my previous post above soon...

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Hit a wall today after I realized the Spartan 3 has nothing in it's library that is tri-state. When I was working with the Spartan 2, it had tri-state buffers. Working with Xilinx CPLD's it was even easier. I think I've hit my personal ceiling at this point attempting to use Spartan 3...

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Edited: The IOBUF is a tri-state buffer, but it's only available on the pads. Looking at the missing line between the memory douta, and the cpu DI, I realize that you're looking for a way to connect those.

There are two options:

1) Use a 3-input MUX, and use the ena signals to select the input.

2) Enable the SSR input on your memories. Tie enable input to '1', and attach inverted enable signal to SSR input. Asserting the SSR will produce a '0' on the douta signals. This way all the douta values will be zero, except for the one memory that you're addressing. Then use an 3-input OR to OR all douta wires together.