2 instructions per word
64K of zero page
32 bit address bus
16 bit word addressing (no direct bytes)

vhdl source
would this be good?
can the free-ip core be modified easily?

cheers

I've often thought it would be nice to have a double-wide 6502. Actually, the 65816 offers a lot of extra capabilities even if you only use bank 0 (the first 65,536 addresses), and I wouldn't want to forgo those. It could be extended so bank 0 (the only bank) is 4GB (whereas the '816 only addresses 16MB directly, in 256 banks). Adding more instructions would definitely be in order. However, I'm not too crazy about what's going on with the 65GZ32 project. That one is not just about a 32-bit 6502. They're getting too far from the simplicity of the 65 family for my liking.

As for putting two instructions in one 16-bit memory location to fetch at once, the advantage would be if they did not really affect each other's outcomes, like TYA, CLC so they could be done simultaneously (not just overlapping). This may not help the performance much though, since a slower clock rate may be needed for the more-complex instruction decoding. Most instructions will have an operand of either 16 or 32 bits, meaning a minimum of two memory accesses (in two clocks) would still be needed. LDA#$4C89 for example would still require two clocks, just as LDA#$89 does now. The 65816 requires three clocks for LDA#$4C89.

Most of what we might discuss on the subject has already been discussed here and on related forums, although not recently; and it still stirs the immagination. Western Design Center is working on a new 65-family processor that I believe does have at least a 32-bit address bus and is supposed to compare favorably in performance to the ARM processors and another family that escapes me right now, but I'm beginning to wonder if we'll live long enough to ever see production parts. They call it the Terbium. They have not released much advance information on it at all.

If you're not familiar with the 65816, I would recommend starting there. Even if you don't think it's enough and you want to head out on your own project, you'll be able to start with more ideas. It still has an 8-bit data bus, but the main internal registers are 16-bit instead of just 8, and can be used in either 8- or 16-bit modes. It has a multiplexed 24-bit address bus. There are long (24-bit) addressing modes, but the data bank and program bank registers can be used to work in the various banks without having to use 24-bit operands every time you want something outside of bank 0. It has more instructions and addressing modes, including ones that make relocatable code somewhat practical, make multitasking much easier, and move blocks of memory. The stack pointer is 16-bit, and zero page (now called "direct page") is relocatable. It's actually easier to program than the 6502 in many if not most cases. It has I/O signals that make certain designs easier, like program and data memory caching, DMA, and multi-processor systems. I haven't worked with it much in a few years, so I'm probably forgetting a lot of things I should mention.

Hi jackokring,
We're running 5 or 6 years late, and it's verilog not vhdl, but maybe the 65Org16 is something like the machine you're thinking of? (I've only just spotted your post)

Here's an index to relevant threads. The CPU is running on FPGA and looks like it should do 100MHz. We have assemblers, a monitor, Tiny BASIC and eForth, and an emulator (thanks to the efforts of several regulars on this forum, this being very much a collective effort and one which builds on several previous projects)

I don't think anyone is presently tackling the idea of two instructions in a fetch, but there's plenty of space in the opcode for composites and the project is open source. ElEctric_EyE is exploring one vision of architectural extensions in his 65Org16.b core.

In fact we did start by modifying an existing core - Arlet's core - which was straightforward. So if anyone wanted to do similarly with a vhdl core, there is now a precedent. It would be preferable to join in on the 65Org16 though!

Cheers
Ed