The STEbus is an 8 bit 20 address line bus based around the Eurocard hardware standard (maybe they had the 8088 in mind when they designed it).

I think this would be a good bus to base a large scale 6502 computer around, even though the 6502 was left out of the specification because it doesn't halt on memory writes (The 65C02 doesn't have this problem). Because it has 20 address lines an MMU could be included in the system.

I don't have easy access to Eurocard prototype boards so I use 100x155mm stripboards for any Eurocard I want to make (it's a close enough compromise). This is what I used for my 8080 project. I didn't use the STEbus for it because I didn't know of its existence when I designed the bus.

More information is at http://en.wikipedia.org/wiki/STEbus and http://www.howell1964.freeserve.co.uk/Arcom/STEbus.htm

The pinout doesn't describe the Command Modifier lines so I'll put them here (they're elsewhere on the site)



I can't get access to http://standards.ieee.org/reading/ieee/ ... 0-1987.pdf which is the complete standard (needs payment, I would gladly appreciate it if someone with access could email me a copy ). I imagine the bus transfers are asynchronous like the VMEbus, judging from the CM lines.

I think it would be tricky to get the acknowledge signal on the 6502's side correct, because if it enters a wait state for each bus transfer it would half the execution time. I've looked into the 68000 processor which uses an asynchronous bus and the acknowledge signals on various SBC's are tied to the /CS pins of the RAM/ROMs (ANDed together), so I think it would be possible to attach a flip flop to one of the phase outputs of the 6502 (probalby phase-1) which, if it doesn't receive an acknowledge within the clock cycle, halts the CPU.

Any comments are welcome.

Thrashbarg.

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Check out my 8080 project: http://kaput.homeunix.org

Search this forum for some of my ideas on asynchronous bus interface ideas. It is possible to interface the 65816 (at the least; not sure about 6502) asynchronously if you're careful with clock sequencing. Obviously, if your clock cycle is too fast, it'll introduce waitstates, but that's the purpose of the asynchronous interface, no?

This bus was amazingly similar to the latest generation of the Kestrel bus specification, only I had provision for the 65816's full 24-bit address bus.

How many STEbus peripherals are commonly available? I may consider going this route for the Kestrel, but the fixed, 16MHz bus clock concerns me, since I will only be running my Kestrel at 4MHz maximum for the time being. Although harmonically related, I may increase the clock speed to 6MHz or 7MHz as parts performance values increase, and these are most definitely NOT harmonically related.

I will need to study this bus in greater detail as time permits. Thanks for bringing it to the fore!

Hmmm...you're right -- information on STEbus is particularly hard to come by for cursory information. Perhaps we should form a community to back the open-sourcing of the bus specification.

One thing that I think needs some clarification is how in particular the ATNRQn* signals are intended to be used. It looks like some serious problems can occur if these are not configured correctly.

I'm curious -- the connector used for the STEbus is said to have rows A and C -- this implies the 32x3 (96-pin) connector was used. Is this correct?

Thanks.

You can get DIN41612 "C" connectors with three rows and the middle one missing, making 64 pins. I used these on my 8080 computer because they were slightly cheaper. There are also 32 pin versions with the middle row and every alternate pin missing.

There's also a DIN41612 "B" connector which is a two row version (i.e. narrower). I don't know if the STEbus uses the B or C version but I guess it's the C connector because that's what the Eurocard standard uses.

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Check out my 8080 project: http://kaput.homeunix.org

Cool -- I think I'll research the "C" version as well, but with all 96 pins present. I'd use the middle row for another 4 address pins, maybe some auto-configuration support, and a few other goodies I've been looking for. That way, older hardware need not be aware of the newer features, and should still be backward compatible.

One more thing -- do you have any information with regards to the bus timing diagrams?

Thanks!

No sorry, only what's freely available on the net. That IEEE document would probably contain it.

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Check out my 8080 project: http://kaput.homeunix.org

Just for your information, I have 6502-based systems on Eurocards on
http://www.6502.org/users/andre/csa/index.html
with MMU, video card, SCSI and more. It uses the "C"-connector
with 64 pins (A+C).

Upcoming soon are Eagle(tm) schematics and board layouts.

André

I have lots of STEbus board manuals (I wrote many of them), and quite a few boards (Z80, SCSI, FDC, 68020) as well.

I wrote the manuals with the content I would want to see, so they have sections for an introductory description, 'how it works', links and options, how to use the board, memory maps, I/O maps, parts lists, circuit diagrams, etc. They would not let me put in the PAL equations but those changed to fix or improve performance.

The STEbus is pretty simple, like VMEbus simplified for 8-bit micros. The VMEbus was very well suited to the 68K, but the signals are sufficiently processor independent for other processors to interface with.

The http://www.howell1964.freeserve.co.uk/ website is long dead but I still have the content growing and awaiting someplace to host it.

So if there is anything you want to know, or a board you would like for testing your board design, mail me.

I'd recommend the SCPUB (Z80 CPU), SPC1 (prototyping card) and SPIBB (two 8255 parallel I/O chips) manuals.

The SPC1 shows how to make a slave board with just a few simple TTL chips.

Bus systems are not so necessary these days because you can get high capacity memory chips/modules that are physically small enough to fit on the processor board. The STEbus supported a 1 Mbyte memory space, and you can get a 512K SRAM chip cheaply.

The /DATACK signal can return at any sixteenth of a microsecond, but if your 6502 were running at 1 MHz then its memory cycles would be extended in multiples of 1 microsecond. This could be a drag if making lots of STEbus accesses but if you have most of your memory on the CPU board (preferable and cheaper) then you only have to worry about I/O access cycles (which are usually a minority).

If you are making a new 6502 design from scratch you can use a modern 65C02 running much faster (say 8 MHz), in which case /DATACK delayed cycles are smaller.

The main advantage of the standardised bus is that several people can develop boards for that bus, and share slave boards. A STEbus floppy disk interface board can be used by any STEbus CPU. That saves re-inventing wheels for every hobbyist's design, and every CPU. This should benefit both 6502 and Z80 retrocomputer geeks equally.

How much storage do you need, Kieth? I can have them hosted if they are under a gig. Got more free but am using for a movie project so a gig can work. Let me know, thanks.

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"My biggest dream in life? Building black plywood Habitrails"

I merged all my stuff, plus stuff borged from other websites, together and I have over a DVD's worth or retrocomputing stuff.

Of course document scans are the bulk of this, and I could easily trim out stuff available elsewhere.

Will I be able to log in and upload corrections / additions as I make them?

http://en.wikipedia.org/wiki/STEbus has had the pinout and signal description added, since this information is hard to find elsewhere.

Hope this helps. If people do design a board to drive the STEbus, I could take a look at it to spot any glaring errors.

DVD is rough, 4.77 gigs. I have 5 total and using a bit. if the relevant ones can be kept to 1 gig, offer still stands there. will get you access if we go for it and all.

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"My biggest dream in life? Building black plywood Habitrails"

But much of it can be found in the wayback machine at archive.org

Specifically, the Arcom manuals and even more specifically STE Bus

Actually, less than 1% of the content can be found via the Wayback Machine. The juicy materials are in the circuit diagrams, and other picture-based figures. All of those are missing completely from the WM's archives.

If folks have the information, I'd be happy to provide some space on my personal computer (which serves my falvotech.com and rezurezu.com domains) to bring these things back to life. Perhaps we can start a WikiBook as well, as a more permanent transcription of the material.