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PostPosted: Sun Oct 27, 2024 6:05 am 
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I have two VIA's and one UART (65c51).
One thing I would like to do is have some jumpers on the board so that you can pick which IC connects to the 65C22's /IRQ and which connects to /NMI. Which would leave the third floating.

If you look at the attached image, you can see that you cannot attach two devices to the /IRQ and you cannot attach two devices to the /NMI. However, you CAN attach the same device to both /IRQ and /NMI. Which would not be desired but I don't think it would damage anything, would it?

Obviously, if there is a better solution I am all ears. One of my VIA's is completely open (both ports are user ports) but the other VIA is connected to a PS/2 keyboard. And of course, the UART is driving the serial connection.

On a side note, I'm only thinking about this because I'm not quite sure where the /NMI should be attached. Since my design involves heavy use of a PS/2 keyboard, I thought about just making that VIA tied to /NMI so it would always process key presses. But I'm not sure how that would work. I saw a design where the guy put the PS/2 clock directly on the /NMI but I'm not sure I want the CPU stopping every few KHz.

Thanks for any suggestions.


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PostPosted: Sun Oct 27, 2024 8:24 am 
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NMI is a get out of jail free card... because you can't disable it, it's always going to respond to a negative going edge (IRQ is level sensitive and requires something to remove the IRQ before the handler finishes, or it will trigger again after the RTI). Which means that in a situation where you want something to which an otherwise unresponsive system to respond, NMI is the way to go.

And generally, that input might be caused by a keystroke. So it's not a _bad_ idea to hang the PS/2 clock signal (negative going!) onto NMI to start/continue clocking PS/2 data into keycodes. However, there's a but (there's always a but). As I and others have discovered, a naive implementation of the protocol can be confused by random data glitches, and get stuck in a continuous loop outputting incorrect keycodes, with no way out.

One way to avoid that is to reset the bit counter if there is too long a delay between pulses (which detects the case where a random bit has started the detection, ten further bits have been received to decode into a false keycode, and a left-over bit has started the next keycode and is waiting hopelessly for more bits), but that generally requires some sort of external free-running timer - perhaps in a VIA.

I think the only issue with your proposed design is, as you observe, the possibility of connecting IRQ and NMI together. That's not a good idea because it will trigger both interrupts, but as it's a hardware link that allows it, it's easy to avoid. But (another but!) a change to software may require a commensurate change to the link; that might be a pain.

Have you considered alternative approaches? All the chips you want to attach to an interrupt have internal registers which you'll likely have to read anyway; if you AND their interrupt outputs together (so the output goes low when an interrupt occurs) you can then easily enquire which chip caused it, and that allows you to tie any number of chips to a single IRQ input (at the expense of a slightly more complex interrupt handler) and allow interrupts from any of them, without requiring any hard links.

Neil


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PostPosted: Sun Oct 27, 2024 11:11 am 
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barnacle wrote:
Have you considered alternative approaches? All the chips you want to attach to an interrupt have internal registers which you'll likely have to read anyway; if you AND their interrupt outputs together (so the output goes low when an interrupt occurs) you can then easily enquire which chip caused it, and that allows you to tie any number of chips to a single IRQ input (at the expense of a slightly more complex interrupt handler) and allow interrupts from any of them, without requiring any hard links.


You can also basically use the VIAs as a programmable PIC if you attach things to the 4 peripheral control lines; or add a 74xx148 if you need loads of devices.

cbmeeks wrote:
On a side note, I'm only thinking about this because I'm not quite sure where the /NMI should be attached. Since my design involves heavy use of a PS/2 keyboard, I thought about just making that VIA tied to /NMI so it would always process key presses. But I'm not sure how that would work.


Someone here recommended to me hanging a single denounced switch off of NMI to use as a debugging "break" signal. Or if you're really fancy, and if your PS/2 is being handled outside of the CPU in hardware, you could make it drive the /NMI when it sees the user press the magic Ctrl+Break combo key on the keyboard.


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PostPosted: Sun Oct 27, 2024 2:17 pm 
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Hello cbmeeks,

TIPP: Maybe you can feed the VIA output signals through gates (made of discrete parts, M²L = Mickey Mouse Logic) with open collectors towards the UART ? That way selection might become a question of programming the VIA's.

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Last edited by L0uis.m on Wed Oct 30, 2024 11:05 pm, edited 1 time in total.

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PostPosted: Sun Oct 27, 2024 4:21 pm 
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Thanks everyone for the suggestions!

I'm going to have a re-think about this and the more I read about it, the more I like the idea of a debounced button for /NMI. Mainly because I totally expect to have buggy code for a while. lol

Then, it would be a matter of simply choosing if a VIA or UART is tied to the /IRQ.

Thanks!

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PostPosted: Mon Oct 28, 2024 2:11 am 
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cbmeeks wrote:
I'm going to have a re-think about this and the more I read about it, the more I like the idea of a debounced button for /NMI. Mainly because I totally expect to have buggy code for a while.

All of my POC units, starting with V1.0, have had NMIB connected to a debounced push button (“panic button”) so I can regain control if the MPU spins out on turn nine.  :D  My usual approach has been to use a Maxim DS1813 to act as the debouncer.  More-recent POC renditions have had some spare Schmitt inverters, from which I could fashion a debouncing circuit.

Attachment:
File comment: Push Button Deboucer
pushbutton_debounce.gif
pushbutton_debounce.gif [ 5.17 KiB | Viewed 195 times ]

The Schmitt inverter in the above may be any of the 74xx14 devices, as long as it is CMOS, not TTL. None of the parts values is critical. The above shows /RST as the output, but that could also be /NMI.  The time-constant of the above is about 250 milliseconds, as it was intended to toggle reset after initial power-on, with reset held low long enough for the clock oscillator to stabilize.  For generation of an NMI, you can reduce the capacitor to 0.47 µF—the resulting ~25 ms time-constant will be more than sufficient.

Attachment:
File comment: Push Button Pulse Generation
pushbutton_pulse_gen.gif
pushbutton_pulse_gen.gif [ 12.04 KiB | Viewed 195 times ]

Above is another circuit, but instead of outputting a continuous low when the push button is pressed, it outputs an approximate 1 µsec low-going pulse at pin 2 of U1a.  A 1 µsec pulse is long enough for the MPU to respond to NMIB at higher-than-1 MHz Ø2 rates, but you might want to increase R3 from 10K to 22K or 33K to lengthen the pulse to accommodate slower clock rates.

A debounced push button triggering an NMI has saved the day for me plenty of times while testing software, especially while developing interrupt-driven device drivers. My POC units’ firmware kicks the system into the M/L monitor if the “panic button” is pressed, making it easier to figure out what went wrong.

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Then, it would be a matter of simply choosing if a VIA or UART is tied to the /IRQ.

If the VIA has an open-collector IRQ output, you can put both on the same circuit, with a 3.3K resistor pulling /IRQ up to VCC.  If the VIA is a WDC 65C22S, then you have to isolate its totem-pole IRQ output from a wired-OR IRQ circuit, using a small-signal Schottky diode, such as an SD103 or BAT85, the latter preferred due to its single-digit recovery time.

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PostPosted: Mon Oct 28, 2024 2:30 am 
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BigDumbDinosaur wrote:
If the VIA is a WDC 65C22S, then you have to isolate its totem-pole IRQ output from a wired-OR IRQ circuit, using a small-signal Schottky diode, such as an SD103 or BAT85, the latter preferred due to its single-digit recovery time.[/color]


Thanks for the information.

After thinking about this last night and today, I think I'm going to just have a jumper to decide which VIA (or serial) would have the /IRQ. As for the debounce, I thought I would just use an ATMEGA328P as I have a little board space and the ATMEGA can do several things.

1) Debounce the reset button
2) Debounce the /NMI button
3) Provide power-on reset
4) Perform reset from button push.

The cost of a DS1318 (or whatever it is) is insane. I really wanted the power on reset which it provides but I think the ATMEGA could double-duty for a lot of that stuff.


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Screenshot from 2024-10-27 22-30-08.png
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PostPosted: Mon Oct 28, 2024 5:46 am 
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Here what I'm doing (in a project that's been collecting dust for a year):
Attachment:
IRQ-NMI-select.gif
IRQ-NMI-select.gif [ 51.56 KiB | Viewed 180 times ]

I have a 3x4 pin header that the shorting blocks go on.  Installed jumpers shown are just examples of course.  The 10K resistors are that high (and could be a lot higher) just to hold their lines high if there's no jumper from a pin in the middle column on the jumper block to the pin on the right.  Jumpering to the left connects the respective IC's IRQ\ output to the processor's NMI\, and to the right connects it instead to IRQ\.  The W65C22S VIAs' IRQ\ outputs do pull up as well, not being open-drain, hence the Schottky diodes, and the high 10K resistances.

The '244 is optional to read a byte telling which interrupt source is requesting an interrupt.

I have a 6502 interrupts primer at http://wilsonminesco.com/6502interrupts/ .  It's one of the very first articles I ever wrote, and the cartoons were almost outdated even back then.

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PostPosted: Wed Oct 30, 2024 8:45 am 
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cbmeeks wrote:
... As for the debounce, I thought I would just use an ATMEGA328P as I have a little board space and the ATMEGA can do several things.

1) Debounce the reset button
2) Debounce the /NMI button
3) Provide power-on reset
4) Perform reset from button push.

The cost of a DS1318 (or whatever it is) is insane. I really wanted the power on reset which it provides but I think the ATMEGA could double-duty for a lot of that stuff.

The ATMEL uC could also provide a 1, 2, 4, or 8 MHz clock. I've used a $2 Nano clone to implement a full-featured ROM Emulator on recent SBC designs (with 'free' built-in EEPROM & Flash ROM programmer). Here's a Ben Eater compatible 8-MHz prototype I just started building up (NO PROGRAMMER REQUIRED);

Attachment:
BE6502-RE Proto Build (b).png
BE6502-RE Proto Build (b).png [ 1.8 MiB | Viewed 111 times ]
Attachment:
Blind Interface Ben Eater.png
Blind Interface Ben Eater.png [ 183.44 KiB | Viewed 111 times ]
Attachment:
BE6502-RE on BB ZIF.png
BE6502-RE on BB ZIF.png [ 540.65 KiB | Viewed 108 times ]


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PostPosted: Wed Oct 30, 2024 2:01 pm 
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That looks great!

I think I asked this before, but what do you use to make those graphics? I really like that look.

As for me, well, I have two different designs going. One is more "old school" but using some modern parts. The other is more focused on SMD and uses a couple Pico's for video, etc.

I'm almost to the point where I will start routing this design. I've always wanted a KIM-1 inspired board but using a large LCD and a PS/2 keyboard.

Thanks


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Screenshot from 2024-10-30 09-58-39.png
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PostPosted: Wed Oct 30, 2024 4:17 pm 
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BigDumbDinosaur wrote:
...More-recent POC renditions have had some spare Schmitt inverters, from which I could fashion a debouncing circuit...

I neglected to mention in my earlier post that both of the circuits I illustrated have their origins on Garth’s site (the first one from the reset page in his 6502 primer).  The second circuit is an adaptation of this circuit—I used it for “clocking” my clock-stretcher test circuit.

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