Hi all.

I'm looking at schematics of the Apple 1, and photos of the motherboard.
At the top left there is an area labeled '6800 only' with no components installed.
I understand that if the CPU is a 6502, that must be the case, but then, where on the card and in the schematic is the generation of the clock signal for the 6502?
It may be to sound as a stupid question.
Thanks in advance.

One of the major innovations in the 6502, believe it or not, was that it didn't need an external clock generator. Chips like the 6502 and 6800 need, internally, a two-phase non-overlapping clock, and prior to the 6502, that meant the expense of an external clock generator. A board which can take both chips needs to have provision for the clock generator that the 6800 needs.

(Of course the 6502 still needs a clock input, but it's a single phase input (almost) direct from a crystal oscillator.)

The clock is being generated by a crystal and two inverters from chip D12 in the terminal section. That feeds into pin 13 of B7 in the processor section (as well as other places), then out of pin 14 of the same IC and into pin 37 of the 6502.

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Bill

Thanks.
Ok. I undertand. I see a 14.3 MHz Xtal on the board, but that I guess it's for the video section. I will to look once more time.
Pleade, do you have a partial Apple 1 schematic shown that Xtal for 6502?

Do you have a link to the schematics you're looking at?

That's the one and only oscillator. Once it leaves C13 it is further divided down by D11. If you look at the schematic for the terminal you will see the little [CL] tag on pin 12 of D11. That is the pricise point that gets fed into B7.

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Bill

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Bill

Thanks - worth reading that thread and following the links within, as there are discrepancies and mistakes to account for.

This NOTE 7 appears in both the schematic versions here (original) and here (Hans Otten).


You'll see one of the solder bridges connects pin 12 of IC B7, a '157, to the clock input of the 6502, pin 37. (Edit: as noted upthread!)

There are an awful lot of signals on that board going through multiplexers, in-line delays, or possibly both...

Neil

Thank you. I was looking at the Terminal Section schematic and indeed the clock for the 6502 CPU is generated from the 14.31818 MHz Xtal-based oscillator, taking advantage of the circuitry necessary for the terminal signals, as you can see on attached figure one. The atached figure two shows on the Microprocessr Section how the phi0, phi1 and phi2 are routed.

I did a little searching and reading... the 14.31818MHz crystal would have been chosen because it's used in colour television and is therefore very cheap and available. It's a high enough frequency for the pixel clock to deliver 40 character text - in the case of Apple 1 that's 7.1909 MHz which is apparently OK on a monochrome TV set but not necessarily on a colour set. It's simpler and cheaper to use a single crystal for everything and have all the derived clocks be synchronous. In the case of Apple 1 the 6502 is clocked with an intermittent 1.023MHz clock (presumably using divide by 14) for an effective average of 0.960MHz. That 1.023MHz is very close to being in-spec for a 1MHz 6502. The intermittency is because the DRAM is refreshed while the clock is stopped, 4 out of 65 cycles apparently.

For more, see for example
https://www.sbprojects.net/projects/apple1/terminal.php

Same in the Apple II. Main xtal frequency is: 14.31818Mhz - Unless you're in the UK/Europe when it's fractionally faster at 14.238Mhz to be more compatible with PAL TV standards.

-Gordon

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Gordon Henderson.
See my Ruby 6502 and 65816 SBC projects here: https://projects.drogon.net/ruby/

Thanks for yours info. Nevertheless I still have the following doubts around the CLOCK control:

In the PROCESSOR SECTION schematic you can see the NO DMA jumper pads. From the factory these pads are soldered as noted in NOTE 13, so the DMA capability is disabled, being the DMA line to LOW state as it is connected to GROUND by the soldered pads. In this case, pin 15 of B7 has a LOW state and depending on the state of its pin 1 (SELECT), you can select between two inputs (13 and 14) to route one of them to output 12 which is the CLOCK signal for the CPU 6502. So, when SELECT on B7 is HIGH, the CL signal going from the from the TERMINAL SECCION, on pin 13 is routed to pin 12 (6502 CLOCK). That is correct, but when SELECT is LOW, the GROUND signal on pin 14 is routed to pin 12, resulting in a LOW level for the CLOCK signal for the 6502. We have this case when the H6 (/HBL) and H10 signals coming from the TERMINAL SECTION are both to LOW level. In short, if H6 and H10 are LOW, the 6502 37 (PHI0) is set to GROUND potential. I don't understand this functionality. Please, could one of you give me an explanation?

Additionally, in the PROCESSOR SECTION schematic you can see above B7 the label 74157/74S257. If B7 is a 74157, when pin 15 is at HIGH level, that puts all its outputs to LOW, which results in a LOW state at CLOCK 6502. If, conversely, B7 were a 74S257, when pin 15 is at HIGH level, that puts all its outputs in a HIGH IMPEDANCE state. This last case isolates the 6502 CLOCK from B7, allowing the CLOCK to be controlled from an external signal from the PHI0 pin on the expansion connector. You can use the DMA capability by desoldering the NON-DMA pads. This allows the DMA line to be controlled externally from the DMA pin on the expansion connector. This is why NOTE 13 indicates that when DMA required, 74S257 be used for B5, B6, B7 and B8.