6502 Reset Vector Internal Logic

[yngbld]

Hi Lads

First time post so hopefully Ive found the right section to ask my question.

I was wondering if someone could explain the internal logic process behind how the CPU locates the reset vector upon startup/reset. What I have gathered so far is upon reset the 6502 will take 7 cycles to load into the PC the address inside the reset vector at FFFC-FFFD.

What Id like to understand, is how does the 6502 know it needs to go to reset vector location FFFC-D without a rom to tell it, is there an internal rom instructing the CPU to go to FFFC?

If somebody could explain the 6502 internal logic process from reset low to reset vector location if possible or steer me in the right direction with some literature explaining the process

it would be greatly appreciated.

Thanks in advance

[GARTHWILSON]

Welcome.  See if this helps:
https://web.archive.org/web/20210405071 ... Tolerances

[BigEd]

Welcome! There are other useful pages on the 6502 wiki: I recommend you also check the index here.

Note first - I think you know this, but to emphasise - that the 6502 doesn't jump to FFFC or any other vector: it jumps through the vector, which is to say it picks up the new PC value from the vector.

The action of each instruction in the 6502 is driven mostly from the so-called Decode ROM or Decode PLA and then the so-called Random Logic which is physically between the Decode and the Datapath. That includes interrupts and reset, which are all handled as variations of the BRK opcode.

When the interrupt, BRK, or reset gets to the cycles where the vector is fetched, there are just a few transistors which modify a default value of FFFF, pulling down one or more of the low bits to construct the right value.

You can watch the reset sequence with a visual6502 URL like this. You'll notice the three bits which control the three LSBs of the vector are called pipeVectorA2, pipeVectorA1, pipeVectorA0

Perhaps see Michael Steil's page:
Internals of BRK/IRQ/NMI/RESET on a MOS 6502

[yngbld]

Thank you very much lads for the welcome and the detailed response BigEd, very much appreciated I'll suss out that visual link and have a read of the recommended text.

Getting a little clearer now I'll shoot back any questions if I get stuck .

Cheer again

[ttlworks]

Welcome.

We happen to have a dissection of the 6509 CPU core here in the forum.
Maybe it provides some additional info.

Edit: clarification:
6509 CPU core is very similar to NMOS 6502 core.
At logic design level, the little difference between both cores doesn't count.

[BigEd]

(I was momentarily confused - that thread is about the 6509 - but of course that's very much like a 6502 for these purposes.)

[Dr Jefyll]

yngbld wrote:

how does the 6502 know it needs to go to reset vector location FFFC-D without a rom to tell it, is there an internal rom instructing the CPU to go to FFFC?

I suggest you focus on the fact that reset executes as an instruction.

As a point of comparison, BRK too is an instruction, and it gets invoked in the more familiar way; ie, in response to an opcode fetched from memory. But reset, NMI and IRQ are instructions that get invoked as a result of a CPU pin getting pulled low. So, it's not necessary to have a Reset, NMI and IRQ opcode fetched from memory (and indeed no such opcodes are defined). But the CPU does execute these with the same general mechanism that supports all instructions. The on-chip PLA and timing logic dictate what will happen during each cycle of the instruction. The shortest instructions require only 2 cycles and the longest (IIRC) is seven cycles. Hope this helps!

-- Jeff

[AndrewP]

I've attached an image of the 65C816 reset sequence. It should be pretty much identical to the 65C02 except that the SYNC signal (synchronise with op-code fetch) is split into VPA and VPB signals on the '816.

In the first picture RESB has been driven high whilst PHI2 was low and the value on the address bus is just whatever was on the bus prior to RESB being driven low.

Each picture was taken after PHI2 went high. On the '816 00 always appears on the data bus whilst PHI2 is low, on the '02 it is not driven.

What is really worth noting is that, as Dr Jefyll has mentioned, reset executes exactly like any other instruction. It starts by doing an op-code fetch (but ignores the result). And then continues like an NMI or IRQ - somewhat similar to a jump to subroutine instruction. It tries pushing the processor counter and status to the stack but remains in read rather than write mode during those cycles.

Finally reset reads from FFFC and FFFD to get the interrupt vector address to fetch the next op-code from. Those addresses are hardwired into the '02 and '816 so no ROM is needed to define them. Someone with a good knowledge of the Visual 6502 could point to exactly where in the silicon they are.

'hope this helps.
Andrew

[EDIT: Label RW is RWB. And AB is ABORTB]

[BigEd]

The three address line pulldowns can be seen here:
http://www.visual6502.org/JSSim/expert. ... 7,686,1193