We sometimes discuss the merit or technicalities of putting two CPUs into a system, with shared memory or otherwise.
Today I learned that Nintendo made such a system, whereby some 33 game cartridges have their own '816-based chip, but clocked 4x the speed of the main one in the console. Both CPUs can send IRQs to the other. The fast one powers up into an idle state.
The faster chip has 2k of full-speed private RAM and a large half-speed (two cycle) RAM and ROM too.
I'm not sure how memory is shared, or how the two CPUs communicate.
The faster chip has extra computation competence too, including multiply, divide, multiply-accumulate as well as other acceleration hardware.
For more, perhaps see
https://sneslab.net/wiki/SA-1Quote:
Nintendo SA-1 (Super Accelerator) is an enhancement chip made by Nintendo, used in 33 SNES games. The RF5A123 chip is based on the 65c816 processor, the same one used by the main SNES CPU, the RF5A22. With identical architecture to the SNES one, the chip is ideal for games and ROM hacks that can reuse code from the main CPU, thus not having to learn an additional assembling language or architecture.
There's a note in there about a 16 bit data bus too, somehow affording faster ROM access.