I'm having a hard time following https://llx.com/Neil/a2/opcodes.html (bold emphasis mine):


The lack of immediate mode for instructions other than LDX does makes sense to me; that would be self modifying code (not that that is always a bad thing :p) Thinking of TXA and TAX as occupying the slots for STX A and LDX A makes sense too, because the spirit of those un-assembleable mmenmonics is the same as those respective transfer instructions. I also agree with the author that the lack of DEC A and INC A are harder to understand, but I am confused why he thinks of the slots as being occupied by DEX and NOP:

• INC A clearly does not do the same thing as NOP, so these instructions are different in spirit: one has an effect, the other doesn't.
  
• DEC A is operating on the accumulator, but DEX operates on the X index register. So the spirit of these instructions is similar but not quite the same; they do slightly different things.

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The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I think there are (at least) three levels of engagement with an early micro like the 6502: there's how to use it, which is the sort of thing the primer is aimed at; there's how it was conceived, or designed, or specified, which is where we get questions about missing instructions or desirable extensions; and there's how it was implemented, which is where we get to understand about some of the 'internal operation' cycles, and any 'extra' memory accesses, and the 'undocumented' opcodes.

I think Neil Parker's Instruction Set Decoded, as linked in the head post, is sitting somewhere in the middle level there, but straddling also the lower level. Which is to say, opcode assignment isn't purely a question of fitting up to 256 values into a big table: to make the implementation sensible, or even minimal, you need regularity in your instruction set and also regularity in the encoding of the instruction set.

But the whole instruction set isn't regular - there are always going to be a few combinations which don't fit in or which don't make sense - so those are likely to be assigned in such a way that the implementation has an easy time decoding them and doing the right actions.

So it's at the lower level - the level where visual6502 is so useful - that we can find answers to this kind of question, I think. Some NOR gate in the 'random logic' area might be combining or modifying some terms in order to produce a needed behaviour.

Studying the machine at this level is interesting, but can also be useful, either to make a compact an efficient re-implementation, or perhaps an assembler or disassembler, or an emulator, or indeed to build some other CPU using what we've learnt.

Nothing like that - just curious I don't think you mean the two instructions that I put after the bullet points above are actually using absolute addressing, because that row is filled in the table. I still don't know why their slots are occupied with DEX and NOP though.
So you do want the self modifying code? Fair enough.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Because if you take %110.bbb.10 (Group 2 DEC) and %111.bbb.10 (Group 2 INC) and %aaa.010.10 (Group 2 Accumulator addressing) together, you get %110.010.10 ($CA) and %111.010.10 ($EA), respectively, as the "natural slots" for DEC A and INC A.

Then when you turn to the actual instruction set, those are not DEC A and INC A, they are, instead, DEX and NOP.

So in other words, DEX and NOP are performed by opcodes that according to the general pattern of group %aaabbb10 instructions would be DEC A and INC A. So the 65C02 ended up locating these useful operations at 000.110.10 ($1A) and 001.110.10 ($3A), where aaa.110.10 is not an implemented address mode in Group 2 in the NMOS 6502 instruction set.

So it's only considered SMC if the first byte of an instruction is being modified? Immediate mode instructions are 2 or 3 bytes long. The first byte contains the opcode, and the second (and third, if there is one) bytes are the constant operand. Where exactly is A going in STA#?


Excellent explanation, kind of like what BigEd was saying about the instruction set not being regular. Thank you.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

The 6800 actually allows it, although I have never used that undocumented feature, and I doubt that it would be easy to find an assembler with that feature built-in.

I also like the 6800's documented ability to do things like LDX 0,X , but it has a ton of weaknesses in other areas to offset that advantage.

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This may be why it might be viewed as nonsensical at a certain level of detail ... it may be that the operation executes by letting the "get the next instruction byte" process run and then grabs the data from the internal register where "the next instruction byte" lands.

In that case, "no, do a write, not a read" would not end up with the data being written to memory, since the "get the next instruction byte" hardware is likely implemented as a read-only process ... and anything written to the internal register where "the next instruction byte" lands seems likely to be over-written by the fetch of the next opcode.

I like jeffythedragonslayer's recent questions. I presume there is an interest to really understand 6502 from the view of a compiler writer, virtual machine implementer and at the transistor level. This question is perhaps the most intriguing and shows a particular thoroughness. In particular, it reveals a binary incompatible 6502 variant with less transistors and more functionality.

I regarded STA immediate as the Technetium of the 6502's opcode chart. It never occurred to me that it has a useful semantic - as implemented by the 6800 designers. As noted in a recent narrated animation about the history of 6502 (and 6800), the designers were very focused on embedded applications, such as automotive. In this context, there is a strict division between program and data. From this view, store immediate is worthless - or even undesirable behavior.

Another example of this code/data separation is the functionality of NMOS 6502 RDY signal which only works when reading. This is sufficient for process control from a cheap ROM. In this arrangement, the system cycle time is limited by the worse path in the I/O segment. If you have, for example, eight RIOTs or ten VIAs, I/O speed is fairly equally matched with the processor. Just add another cycle or two to cover slow ROM. That is more adequate for stepper motors and similar. However, if you want the fastest, general purpose computer and you want to interface 2MHz processor with 1MHz peripheral, a RDY signal which is ignored during write cycles is an annoying impediment.

It was corrected in 65C02 but this only makes a three way corner case. (RDY stretching, write cycles, NMOS: choose any two.) Unfortunately, I've been affected by this problem. Despite expert advice, people insist on using dodgy, random components. Therefore, I've made sure that my work is NMOS compatible. This is quite easy in software. Like the 6502 designers, I was concerned about NMOS compatible slow ROM access. Unlike the 6502 designers, I didn't clock stretch I/O correctly. It is a regrettable decision made downstream from the 6800 and 6502 design decisions. It was caused because I wanted maximum performance rather than a cheap and cheerful system.

In the very hypothetical situation of designing an 8 bit instruction set where more than 1/3 of the opcodes are unused, I'd probably leave STA immediate unallocated and put all of the fiddly exceptions (LDX#, LDY#, INX, DEX, INY, DEY, CLV) into one group. I'd also make RegX and RegY down counters so that DEX and DEY would be one cycle. However, that probably requires more transistors.

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