This week, 1985, and NASA is hooking up as many as four AM9511 FPUs to an AIM-65 computer and manually scheduling the overlapping FPU activity to meet a 20ms hard realtime deadline. It turns out the 9511 - or Intel's licensed clone, the 8231 - is not terribly easy to hook up to a 6502 system, especially with the RDY signal not affecting write cycles and with the occasional spurious address during indexed instructions. So the researchers used an HP9845 desktop computer to simulate the bus timing and ensure that all was well. With four FPUs they could reach 1/40th of a MFLOP, just a little better than an 8086 with 8087 coprocessor. The NASA report is here:
https://ntrs.nasa.gov/archive/nasa/casi ... 026198.pdf
(includes schematics and some code)
...
They note that up to 10 FPUs could be usefully connected, if trig functions dominated the workload. They also note that Forth would be a win compared to Basic, for performance, but pure assembly code is fastest - not surprising really.

They also note that the 1981 MICROCRUNCH project as published in 6502 Journal might have been a better approach, had they known of it! It was an expansion for the OSI Superboard but surely could be adapted:
http://archive.6502.org/publications/mi ... pdf#page=9
Part 2:
http://archive.6502.org/publications/mi ... df#page=85

Finally, see here for a 1983 FPU card for the Apple II, by Redshift:
viewtopic.php?p=42946#p42946