Over in the Space Shuttle thread (aka 6502 in Spaaace!) tokafondo shared some findings among NASA documents, and in particular found a patent for a memory extension scheme, by Gordon Wiker.

It's an interesting scheme, and I'm not sure we've seen quite the same thing here before. Edit: I think it's different from Jeff's scheme as seen in KimKlone...

Here it is:
- a handful of zero page locations are decoded and implemented by additional hardware registers
- when an indexed instruction is detected (by SYNC, as usual) which uses a zero page location in this range, things happen
- optionally, the fetch of two bytes of pointer is redirected to the additional memory bank specific to this zero page pair
- after the index addition, the memory access is redirected to the additional memory bank specific to this zero page pair

The bones of it, then, are that specific zero page pointers will point to specific memory banks. This isn't a means of running code in a larger space, but a means of accessing larger data sets.

The patent notes that it will be convenient to the programmer to keep the pointers in the main memory - that is, not use the option to fetch the pointer from the appropriate auxiliary memory. It's easier to modify the pointer in this case. On the other hand, if the pointer is in the extended memory, it doesn't take up zero page space.

The patent notes that their choice of decoding (zp),Y is just one of many possibilities. (I notice there are no RMW opcodes to worry about in this case: there's exactly one indirect access to be redirected.)

Edit: it might be worth noting that there's no MMU, or place to store the chosen additional memory - the particular additional memory is tied to the particular zero page pointer.

The patent is 4,481,570, and NASA's page on it is here.

Edit: they use LAB and HAB to denote the low address byte and the high address byte.

(It's a 1984 patent so the whole point is that this documented technique is now free for anyone to use.)

The 6509 used the lda (zp),y and sta (zp),y instructions for extended data access, and zero page locations $00 and $01 to set execution and data banks. The method in this patent seems similar, but using external circuitry, and limited to data bank only. The main similarity to the KimKlone scheme looked to be the opcode recognition and the involvement of external, as opposed to the 6509 which does it within the CPU.

Similarly, Acorns's "6502 Turbo" uses a similar method.

When enabled, any (zp),Y addressing mode fetches a byte from &0300+zp to use as b16-b23 of the base address.
Eg, if
&00FD=&00
&00FE=&80
&03FD=&04
then LDA (&FD),Y fetches from &048000+Y

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What I would like along those lines would be a zero page memory location (say, $0000 or $0001) where you write a byte which has two nybbles, one for the extended memory zone for (zp),Y addressing and another for the extended memory zone for (zp,X) addressing. So if it contains $34, then $30-$3F accesses by a (zp,X) instruction go to the alternative memory, and $40-$4F accesses by a (zp),Y instruction go to the alternative memory.

The implementation might be easiest if the system is based on a 128K SRAM, so all that the "external memory" implementation must focus on is whether to pull A16 high or low.

Out of 6509, Acorn Turbo and Dr Jefyll's most famous curiosity, US Patent 4481570 appears to be most similar to Acorn Turbo. The major difference is that US Patent 4481570 appears to be restricted to a subset of possible (zp),Y accesses. I presume the patent was granted after Acorn implemented a similar system. However, was the patent filed before Acorn's implementation?

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