Hello! Can anyone analyze in machine cycles the command:

1234 JSR $1000

I don't understand what you're asking. According to the documentation, that instruction will take 6 cycles. Three are used for fetching the full instruction, two are used for pushing the return address on the stack, and one is a CPU-internal cycle that does nothing visible on the external bus.

First of all, thanx a lot for your time. I hope the next example will help you understand what I want.

For example, if we had

100 LDA $1234

than the answer would be:

Phase AB DB Internal operation

1. 0100 LDA PC<-(PC)+1, therefore (PC)=101
2. 0101 34 PC<-(PC)+1, therefore (PC)=102
decoding of LDA
3. 0102 12 PC<-(PC)+1, therefore (PC)=103
4. 1234 (1234) MDR<-(1234)
5. 0103 next opcode PC<-(PC)+1, therefore (PC)=104
ACC<-(MDR)

Oh, I see. There is a breakdown of the cycles in WDC's 65816 book, which applies also to their 6502. I don't know if it matches 100% with the original NMOS 6502 though.

I don't have the book in front of me at the moment (I'm at work), but if I remember, I'll post the details of JSR for you. I do recommend grabbing their copy though -- it's available here:

http://westerndesigncenter.com/wdc/data ... manual.pdf

IIRC, that book includes a 65816 datasheet in it which has the cycle breakdown. Otherwise, you might want to check here: http://www.6502.org/documents/datasheet ... b_2004.pdf

Thanks.

The WDC 65C02 datasheet also has a cycle breakdown, starting on page 32. (Feb 2004 version).

Daryl