Jmstein7 wrote:
Write Data becomes valid some time after the positive edge of PHI2, and Read Data becomes valid thereafter, when PHI2 goes low again.
I hope it's clear that, in terms of timing, the datasheet describes what the CPU does but it also describes what the CPU
requires -- IOW, what the
attached circuitry (memory and IO) must do. Perhaps there's no misunderstanding, but for clarity l would rephrase the second part of your statement to say, Read Data
is required to be made valid thereafter, just before PHI2 goes low again. IOW, the CPU doesn't make read data valid; it's the device being read which does that. And it must do so in a way that meets CPU timing requirements.
65(c)02 bus timing is substantially same as '816 bus timing. That applies to how A15 - A0 change in the first half of the cycle, and also the activity on the data bus during Phi-2 high -- the read data and write data. So, one doesn't need to re-learn that stuff. The big contrast is the data bus during Phi-2 low. An '02 or 'C02 always "floats" (tri-states) the data bus during Phi-low, whereas the '816 always outputs the Bank Address during Phi-low. This is true even in Emulation Mode (although in Emulation Mode the Bank Address defaults to zero).
Quote:
So, how in the world does one properly set up /OE, /CE, and /RW for, say, a bank of 32K of ram
Generally speaking, with '816 your main concern is to ensure that no memory or IO device drives the data bus during Phi-2 low. But otherwise you can pretty much treat the '816 as you would an '02 or 'C02. Note: the '816 will be noisier, so good construction techniques and supply bypass caps become more important.
-- Jeff
_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
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