The 6502 on-chip circuits to generate the clock signals phi1/cp1, phi2/cp2/cclk and "phi2 pullup" (in the terminology of BreakNES) each appear to be duplicated. I assume there is an important analogue reason for this. Can someone explain or point me to a previous post on this?

_________________
Davidmjc

Is it just a question of parallel driver transistors to provide greater drive? If not, maybe you could say more about what you see compared to what you expect.

In the case of phi1 and phi2, it seems one copy of the circuit is used to drive the phi1/phi2 pad, and another to drive the internal phi1/phi2 circuit, while for the phi2 pullup, the two copies (see attached) feed into different parts of the control lines circuit.

_________________
Davidmjc

Ah yes there is something interesting going on there
http://visual6502.org/JSSim/expert.html ... 0&zoom=8.9

It's rather redundant, as you note. That might just be for drive, but maybe it's a bug fix or simplification.

The primary onchip phase 1 clock, cp1 in visual6502, is inverted to produce nodes 43 and 1247, which each drive a selection of logic gates conditioning the datapath control lines.

The inverters are laid out somewhat like NOR gates, but with both inputs driven by the same signal. So we have two inverters, with very strong pulldowns, inverting the same cp1. It might be like this merely to provide enough drive, but I do wonder if those NOR-like layouts were originally combining two signals.

Balazs only includes one of these lines in his schematic of the Rockwell (labelled "bar cp1"). Was only one in the Rockwell? Are both needed? For the cp1 and cp2/cclk cases, I suspect that I answered my own question, in that one might want the circuit driving the pad and the circuit driving the internal bus to be independent, but I find it strange that this is done by repeating the creation of cp1 and cp2 from cp0. Or maybe this is the best way to create the most faithful replica signal on the pads?

_________________
Davidmjc

My theory is that there are logically two separate functions covered by the clock generator:

1: Driving the external timing element connected between Phi0 and Phi1 pins, and driving externally timed logic hung off the Phi2 pin (notably, devices like the 6522 VIA).
2: Distributing the internal timing accurately across the intricate logic elements of the chip.

MOS probably wanted these two functions to avoid interfering with each other as much as possible. So Phi0 was taken as the common timing reference, and the internal and external clock generating inverters were physically divided. This avoided having the external pins delayed by two gates from the internal signals, or vice versa, as might have happened if one set of signals was directly derived from te other through a drive stage.

Another point that's easy to forget is the 6501, which required an external two-phase clock in the same way as the 6800 did (for pin and system compatibility). The MOS design would have had a mask option to disable the external portion of the clock generator, and derive the internal signals from the externally supplied clock. Motorola put a stop to 6501 sales by legal means, but the externally-clocked option resurfaced in the form of the 6512.

Certainly good points: the 6501 option, which requires changes only to the contact cut mask, and also the possible advantage of isolating onchip vs offchip signals.

For the datapath driver control signals, I've taken a clipping from Balasz' giant stitched photo of an R6502, and rotated it to match the visual 6502 orientation. I haven't yet stared hard at it.

Thanks Chromatix- that makes sense, both the accurate timings and the independence of the circuits. For the datapath controls, the Rockwell looks the same as the Visual6502 to me (and it would be surprising if they changed such an intricate detail!). I guess the explanation here is again independence and accurate timing: one of the clock signals grounds the outputs of the control line drivers, the other grounds the inputs. Maybe the former ensures sharpness of the cut-off, while the latter reduces power consumption?

An interesting curiosity is that for the X Y and A register outputs to SB and DB, not-cp1 grounds the outputs whereas cp2/cclk grounds the inputs. This is done differently for the stack pointer because of the separate S/S control.

_________________
Davidmjc