Hi all

I once read somewhere that there are versions of the 6502 - embedded in various chipsets - that run >100x faster than original CPU. Is this true? What's the fastest implementation anyone knows of?

And what's the fastest implementation available in an FPGA? I know that the MEGA65 is 50x faster.

For context, I am working on a 6502 compatible system in an FPGA and am curious about the state of the art. So far my design runs at 50MHz (although this may drop to 40MHz because timing closure is really tough). It also offers better IPC, with a throughput of 1 instruction per clock for everything except read-modify-writes and indirect jumps (which take 2 cycles).

Thanks!

Welcome! WDC licenses models for companies to build 6502 from, and I imagine it's one of those licensed builds which is touted as going so fast.

FPGA 6502 running at 50MHz isn't bad - it's certainly possible to do better, and of course it depends on how new and how expensive the FPGA is. And well done, a more cycle-efficient core will get an advantage.

The fastest 6502 these days, I'm fairly sure, is an emulated 6502. This is because of the great pressure on performance of general purpose CPUs, and the great price advantage of volume. A $10 Raspberry Pi can emulate a 6502 at around 300MHz, and a Pi 4 goes even faster. The PiTubeDirect project allows a Pi to be connected to (or in) an Acorn BBC Micro, where the Pi can act as a second processor, in a historically authentic way. It looks, feels, and acts like retro computing with a 6502, even though there's an embedded emulation involved (as well as a genuine 6502 and much TTL).

Thanks.

I have found some corner cases that make high clock speeds (>50MHz) really difficult, self modifying code and decimal mode being examples (self modifying code really interferes with pipelining). That's what got me looking at better IPC at more moderate clock speeds and with a shallow pipeline. The design fetches up to 4 bytes of code and reads/writes up to 4 bytes of data in parallel per clock. I also had to add a small cache for zero page and stack so that ZP pointer fetches and multi-byte stack pulls can happen concurrently; LDA/STA indirect indexed, JSR and RTS are all single cycle.

I'm aware of the emulation options but my focus is FPGA. My project is closely related to the BBC micro - I hope to produce an enhanced clone of that machine as part of it.

Sounds very interesting!

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

From experiments in the past, I hear that a 6502 on the -2 speed grade of a Xilinx LX9 can work at 100MHz, although it didn't quite meet timing according to the tools. (Edit: the -2 speed grade is slower than the -3 grade.)

I think FPGAs are quite exciting enough, and affordable enough, and fast enough to work with, that we don't need to dream about custom chips.

A quick update on this. My CPU (which I am calling "e6502" for now) passes Klaus Dornann's functional test and meets timing at 50MHz. I still have a bit more verification of decimal mode to do.

I have a simulation setup which runs the test code on my CPU and also on the well known T65 core from the FPGA arcade project; it compares the registers of both at every instruction boundary and there are no discrepancies.

Here are the figures from a full run:
instructions executed: 30,646,177
clock cycles (e6502): 30,960,983
clock cycles (T65): 96,241,366
cycles per instruction (e6502): 1.01
cycles per instruction (T65): 3.14

So the e6502 is performing like an original 6502 clocked beyond 150MHz.

I have checked my 6502D implementation which I use for the "MockA65xx" project
on an DE10 FPGA Board running and the Dormann test suite at 100Mhz without problems...

... next time I've git my test setup running I'll try to clock it higher.

Did you ever publish this new core, amb5l? Getting it to pass Dormann's tests is a very good sign.