Hello All! It's been a while (> 1 year). Good news, the back surgery in May 2018 was a success, no more sciatica. But life changed for me when when I we lost my father that previous month. I've become pretty good at installing electrical services, plumbing, air conditioning etc. I can even shred a field. I am not the geek/book worm my father knew anymore. Then a move from Irving to Dallas, and now Diesel, the farm dog is a big city dog.

I am trying to get back into electronic again. Still kicking around some ideas. I have been lurking here for a bit, and there was a recent topic about pipelining.

CMP and B?? give me a headache. I have to keep referring to:
http://www.6502.org/tutorials/compare_beyond.html

And so I have been thinking. What if we had a new instruction:
BMP MINUS, PLUS ; MINUS is a relative offset to code for the MINUS situation and PLUS is the address of the PLUS code. Falling thru would be EQUAL.

Would something along those lines improve efficiency? I would think it would avoid a pipeline stall and save a cycle or 2.

This community is the best. Thank you to each one of you.

Walter

Nice to see your electronics interest is on the rebound, Walter, especially after the ups and downs you describe!

So, the instruction has three possible outcomes, if I understand properly -- offset A, offset B or no offset at all.

Re pipeline stalls, are you speaking in context of the thread Pipelining the 6502 ? If so, I'd say the key issue is branch predictability. If a program is such that the branch result tends to be the same every time then the Branch Prediction logic will generally be accurate, and stalls will be avoided. But if the result tends to be fairly random then predictions will often fail. That's true for ordinary branches as well as for your proposed branch -- so, it's doubtful whether there's much advantage in regard to avoiding pipeline stalls.

But it sounds as if your proposed branch would offer other advantages, such as shrinking the code size. In any case it'll be necessary to have an unused opcode which can be assigned.

cheers,
Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

I am reminded of FORTRAN's three-way IF, but I can't remember if that was just a coding "convenience" or if it actually mapped well to the underlying architecture.

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Got a kilobyte lying fallow in your 65xx's memory map? Sprinkle some VTL02C on it and see how it grows on you!

Mike B. (about me) (learning how to github)

Yeah, maybe pipeline was a bad choice of words. My logic says having the PLUS and MINUS relative offsets already available would possibly help instead of having to do another instruction fetch and decode. But I will take that as validation of my concept

I just wish I could find a cheap 5 volt safe FPGA.

Walter