I'm a bit confused about how the 6502's ALU performs increments. I've been attempting to understand the output from Visual 6502 along with Hanson's Block Diagram. Thinking logically I'd expect one side of the ALU to have the value of X/Y-Register loaded, and the other to have the value 1, which are then added together. However there doesn't appear an obvious way of generating a 1.

Here's what I think happens based on this snippet from Visual 6502 - XSB,SS,nDBADD,SBADD,SUMS:

The ALU gets its A input from the X-register via the SB, and the B input gets a 0 by putting the pre-charged DB (FF) through the inverters (00).
(Since there don't appear to be any Open Drain MOSFETs on the DB I'm assuming that the Pre Charge FETs on the DB can only generate an 0xFF?)

If this is the case, where does the missing 1 come from to complete the equation A + 0 + 1?

I'd assume the Carry In signal (I/ADDC) would come into play, so the ALU would perform A + 0 + C. Only problem is I can't see I/ADDC anywhere in the Visual 6502 output for INX, nor can I find any reference to setting the C-bit of the Status Register (P).

Related:
- What exactly does the I/ADDC signal do? Does it put a 1 into the carry in of the ALU, or does it enable the value of the P's C-bit into the ALU?
- When the ALU performs addition during an ADC or SBC instruction does it query the C-bit directly from the status register?
- I'm guessing that INX/INY don't use the P's C-bit since the instruction doesn't affect it, even if incrementing FF

Thanks!

Welcome! You're very close. Indeed, the ALU input can be forced to 0 or to FF, and the alucin signal is controlled in such a way as to set the carry for increment. In the case of an ADC, the alucin signal would be derived from the C flag. There's a 4-input NOR gate here which ultimately produces the carry in, and the four inputs, if you traced them back, would hopefully correspond to all the expected cases (adc, sbc, inc, dec presumably, rol, ror, at least.)

It's possible to trace signals back in the source files, but I usually trace them visually in the layout. That's an acquired skill!

Thank you BigEd. It's good to know that my understanding of the Visual 6502 output is on the right track! I took a closer look at the op-codes for all the ADC and SBC variants, which will make use of the C flag. Turns out they are all uniquely identified by the bitmask x11xxx01. I'll do the same for the IN_ op-codes, which require a forced 01 and see if there's a similar pattern.

Christian

If you look at the 6502 opcode map you'll see almost every opcode fits into a bitmask pattern. INX/DEX/INY/DEY not so much.

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JGH - http://mdfs.net