Basically I took screenshots of Visual6502 and put them together to a big picture. Then I drew the schematics on a new layer based on that picture. It might be hard to read due to how messy it is, which is result of the way the different materials were placed on the chip. I was planning on making updated version that is cleaner (such as removing lines for control signals and entering their name next to the mosfets that use them. Secondly clean up the wiring on some parts to make them easier to follow. The possibility of mistakes are there, but I did take the time to carefully go through everything, so I hope it is good enough. I originally started this to learn reading the visual circuit simulations better, so the end result as is might not be the most convenient for to be used as a schematic.

Just as a side note. The image is well over 5000x5000 pixels in resolution, so I guess low end PCs might struggle opening/viewing it.

Wow - that's a major effort! Well done. I'm interested, of course, in any questions or observations that might come up.

Brilliant, thanks!

-Gordon

_________________
--
Gordon Henderson.
See my Ruby 6502 and 65816 SBC projects here: https://projects.drogon.net/ruby/

Here is the cleaned up version that has cclk, cp1, control lines and few other lines replaced with labels. Especially the ALU became much clearer to read. I also filled in few small spots that I missed from the first version

Thanks for posting, FreyFox. Welcome to the forum!

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

I started re-arranging parts to make readability easier. I started questioning what type of mosfet the one in the picture is. Looking at that there is a loop it would seem enhancement mode, but that probably would send constant voltage to the circuit. Depletion mode would seem more logical, but then again a loop like that usually indicates an enhancement mode mosfet. Which one is it?

There are, I think, several things of interest here.
http://www.visual6502.org/JSSim/expert. ... &zoom=10.4

The first thing is the pad, a large metal structure for the bond wire to land on, which you've labelled rdy.

To the lower right of the pad, we see we have polysilicon sitting between the rdy and vdd, and connected to rdy. So that's a pull-up.

To the left and top of the pad is a snaking diffusion track. That's a resistor (usually).

To the lower left of the pad, there's a magenta polygon, between rdy and ground, and that's a protection diode. The resistor and the diode provide some protection against overvoltage and static damage.

To the right of the diode is the bit of interest to a logic-level simulation: the poly from the pullup forms the gate of transistor t475 in an asymmetric U shape.
http://www.visual6502.org/JSSim/expert. ... 3&zoom=5.0
This transistor is the pulldown for node 958. The pullup is just below, and the overall effect is an inverter.

The pulldown for the inverter is strong (the poly snakes a long way) as is the pullup (very short and wide poly forming a transistor to vdd.) The ratio between the two can tell us the switching threshold of the inverter, which we'd expect to be skewed so it responds to TTL levels (when taking into account the protection resistor, probably.)

To answer your question, then, the pullup you've circled is most likely a depletion mode device. It acts as a pullup, but whatever chip on the outside is driving RDY will be able to drive the node low.

So, the pull-up isn't alone strong enough to trigger the pull-down and requires signal from RDY to drive node 958 low?

It looks possible that the on-chip pull-up on the rdy input will mean that an unconnected rdy will be taken as a high, which is the state where the processor runs normally. If a driving chip is connected, it will drive the input in the usual way. (I wouldn't expect to see an open collector driver used here)

In any case 958 will be the inverse of rdy.

For 958 to be inverse of rdy, the only way that would seem to be possible (according to a simulation) is that when rdy is low, the voltage provided through the mosfet I circled is driven out through the rdy pin and possibly to a ground outside of the chip. I'm not sure if it was intended to work that way, since rdy seems to be considered as an input pin.

Indeed, this is how an external chip drives low: it sinks current. In effect the driving chip when driving low is like a resistor to ground. The pin voltage will drop and when it crosses the inverter's logic threshold the output of the inverter will go high.

Sometimes one can figure these things out with logic levels sometimes with voltages and sometimes with currents.

It's crucial to note that current flow is not the same as logic flow.

Next update.

Mostly cleaned up random control logic from input lines (PLA labels) and output lines (RCL labels). As usual found few incomplete spots and few errors that I fixed. The schematic starts looking fairly readable. The only thing is that the PLA lines can't really be described with short enough lable to use the same ones Visual6502 uses. That would help a little bit as well.

By the way, Visual6502 has few nodes named D1x1, H1x1 and C1x5Reset. Where do these names come from?

I think those names from from Balazs' giant schematic, which predates visual6502 and is a wonderful piece of work, although slightly incomplete.
http://www.visual6502.org/wiki/index.ph ... _documents