Hello. I recently stumbled upon a YouTube video about a presentation event on the reverse engineering of the 6502 processor. Somewhere in that video, the speaker included a transistor level schematic diagram of the 6502 in his presentation. I looked it up myself on the real web successfully and upon closer inspection, while I'm confident that they are MOSFET transistors, the question is what type are they? What does the thick gated transistor represent compared to the thin gated ones? And what are those mini transistors? Or are they switches? As an example, here's a model of the clock generator circuit for the 6502 using the transistors I'm talking about.
I'd like some help here. Thanks!

All of the transistors are N-channel MOSFETs. The NMOS process simply doesn't have any P-channel ones. I think they're using a symbology in which a P-channel device would have a circle at the gate.

The ones with thick channels are doped into "depletion mode" and are used like resistors or constant-current sources.

The size of each transistor is probably related to their physical size on chip. The input buffer uses small transistors since they don't need to drive much, then the four on the left are big drive transistors to send the clock pulses across the whole chip. Those clock signals interact with many other circuits, so they need a lot of drive power.

Welcome, Tompis1995!

Agreed with Chromatix' points. These diagrams are almost certainly from Beregnyei Balazs' reverse-engineering work: the layout of the schematic follows the layout of the transistors on the chip, although it's upside-down compared to the usual arrangement, probably because of the microscope inverting the image.

Some links and info here:
https://web.archive.org/web/20210405071 ... _documents

Edit: fix link rot

Also, I see an intersection of one line going from the drain node of a depletion mode transistor to the source of an enhancement mode transistor and a line connecting to the gate of the depletion mode transistor. Does that mean they are connected? Because the rest of this picture has notable dents in the wires indicating a jump over.

Yes, a standard feature of this process (which was an innovation by MOS at the time) is for depletion-mode transistors to have their gate connected to their source, causing them to act as constant-current pull-up loads. This was a much more efficient use of die area than the long, thin wires previously used as resistive pull-up loads.

Indeed - the modern style is to have a blob where there's a connection, and an unadorned crossing is just a crossing with no connection. The old style, as seen here, is to have a jump over when there's no connection, and a crossing without a jump is a connection.



Hmm, I don't quite agree. MOS Technology were indeed among the first adopters of ion implantation as a way of adjusting transistor thresholds, and so they could and did use depletion-mode pullups. But the previous technology was enhancement-mode pullups with their gates tied to a rail - either the Vdd rail or an elevated rail. I'm not sure they were larger, but they were much less power-efficient. Or, more power-wasteful. They also pulled up only to a threshold below the rail, which made for lower logic levels and is the reason why the 6800 and similar need an off chip clock driver.

Long thin wires are generally used for resistors in analogue circuitry, then and now. I'm not sure I've ever seen them for pullups in logic gates.

Two more questions:
1. Why is there a ground wire connected to the gate of one of those small transistors?
2. Based on this configuration of the transistors, how would I translate them to logic gates?

The grounded transistor acts as a diode - a protection diode for the input pin.

To make logic gates, start by looking at each of the pullups. There are four depletion pullups. Look then at the pulldown networks: a single transistor means it's an inverter, a pair in parallel makes a NOR, a pair in series makes a NAND. Then you can look at the non-depletion pullups. These are usually in a super buffer configuration: a pullup whose gate is controlled by a signal, rather than being controlled by its own output. In this case, we see four pairs of transistors, each a pullup and a pulldown, being driven more or less by a signal and its inverse. Each pair is logically an inverter, it's just that the pullup is actively controlled rather than being a depletion-mode device. Superbuffers are used when you need more drive, and as these are the internal clock signal drivers, they need a lot of drive.

I now have another issue. Somewhere on the diagram, there are these intersections shown in this picture. How should I know which ones connect and which ones jump over? I marked the intersections in 3 different colors for individual reference.

All three of the marked intersections are connections. As previously noted in this thread, this is an older style of diagram which doesn't have an explicit blob on connected intersections.

Wires which cross without intersecting have a "bridge", as seen with the many wires crossing DATA1 and ADDR1 towards the left of the section shown.

I see. But, how should I know which direction the current is flowing at? It appears as though current would easily flow to the drain of a transistor.

Current flows in the opposite direction to the movement of electrons in the metal, which are attracted by high voltages and repelled by low ones. That really is the essence of electronics.

You can do a lot of interesting things with switching circuits: relays and pass transistors can both be used, and in the case of 6502 there are at least two sets of 8 pass transistors which are logically bidirectional: they connect two busses, and if the one bus is driven high or driven low, the value is propagated to the other, in both logical directions. Note that current flow could be in either direction: to drive a zero, you need to discharge a voltage, so current flows away from the node which needs to go to zero. And vice versa to drive a one.

Don't worry about electrons: that's a step too far!

It is one extra thing to learn though: in the logic gates, transistors are either pullup or pull down and you can ascribe them a source and a drain. When FETs are used as pass transistors, they are truly bidirectional. You can choose to think about currents and voltages, but most of the time you don't need to. It's enough to think of them as switches, either connecting or not connecting the two sides, according to the state of the gate input. It's enough to consider just high voltages and low voltages, for most cases. You don't have to think of voltage as a continuous variable: just high or low.

Clarification: logic levels are defined partly by the technology. In the past, they were not always positive voltages. In the late 1960s Westinghouse manufacturered and supplied control equipment that operated from a 18V DC power supply. One logic level was 0V. But the other logic level was between -16V and -18V. Trying to read the schematics (which use different symbols as well) gave me a headache when I first tried...

Mark

Indeed, when you've trained your brain on high voltage meaning logic 1, and on NMOS transistor behaviour, trying to understand circuits which use other conventions is a bit disorientating. But while this is true, isn't a huge distraction to someone just beginning to get to grips with circuits found in the NMOS 6502?