For those of us thinking they were really ambitious trying to build a 6502 SBC out of little black boxes -- a gentleman by the name of Robert Baruch is building a RISC-V processor out of LSI logic. Yes, a 32-bit processor with 32 registers.
Quote:
The LMARV-1 (Learn Me A Risc-V, version 1) is a RISC-V processor built out of MSI and LSI chips. You can point to pieces of the processor and see the data flow. It should be a nice way of demonstrating how RISC-V works and how simple it is to implement.
He has uploaded a fascinating video
https://www.youtube.com/watch?v=yLs_NRwu1Y4 about the first steps, including a (brief) introduction to the RISC-V open ISA CPU, and a discussion about why he chose what chips. It's nice and hardcore, involving things like back-planes and clock signals, resistance values and PCB suppliers. I'm sure some other people here will love it as well.
Oh, and it has blinking lights. Gotta have blinking lights.
For those who haven't heard about RISC-V before, it's a "free and open RISC instruction set architecture", see
https://riscv.org/. It's been mostly theoretical so far, but now there is SoC out at
https://www.sifive.com/products/hifive1/. Western Digital has announced it will be using, oh, two billion of these things in future hard drives (
https://www.anandtech.com/show/12133/western-digital-to-develop-and-use-risc-v-for-controllers) and Nvidia is looking to use the architecture for their microcontrollers on their graphics cards (
https://www.phoronix.com/scan.php?page=news_item&px=NVIDIA-RISC-V-Next-Gen-Falcon).