You mean the guys who made a processor published benchmarks that showed it was faster than their competitors' processors? No! Say it isn't so! Surely they were not biased in the benchmarks that they chose!


Well, write a re-entrant routine to which you pass the address of a data structure like { word input_buf, byte curpos, word output_buf } which accesses all of those, and show me how the 6502 code is better. (You may think that this example is slightly contrieved, but it routines like this do exist. My point being, "much better" depends on what you're doing.)


Not really, no. They would have been on the 6800, but the 6502 could have gotten by quite well with just one index register, Y. It's worth thinking about why this is.


I'd love to see your original source code for this. Did you seriously, with every use of indirect jump, have something in place to check for and handle the wrap-around, should it be present? What did this look like? If your code just did a `JMP ($nnnn)` with no extra information about alignment, you were a victim of the bug, hoping rather than being sure that it never wrapped.


Yes. For the reasons I explained.


Ok, I checked it; I see nothing about any kind of "lock." Did you have a specific part of that article in mind?


And IMHO it was not. Do you have any evidence that it was "protected?"

Having been there at the time, I certainly am not surprised that the Spectrum, Amstrad CPC and MSX did not do well in the North American computer market of the early '80s. By that point, diskette drives were a common and expected peripheral in North America and software was expected to come on floppies. The first two above distributed most of their software on cassette tape, and the last on expensive ROM cartridges.

My first serious part-time job in 1985 and 1986 was at a consumer computer store in a shopping centre in a suburb of Vancouver, B.C. We sold a lot of Commodore 64s, and I don't recall ever selling even one without a diskette drive. Had anybody asked to buy one without, I would certainly have told them that that was a bad idea.


Well, I guess we'll have to agree to disagree. But when you have a pin on the processor specifically for setting the overflow flag, having an instruction to clear it after handling that input makes sense to me.


It doesn't matter how fast JMP is; code with JMP is not relocatable without being patched up. Go write some code designed to be relocated and you'll understand how useful BRA can be. You'll note that this is one of the instructions that they added in all of the CMOS versions, and for good reason. (It appears to have been left out of the NMOS version merely because they didn't want to add a ninth branch instruction, which makes sense when you consider the significant additional logic that moving from eight to nine branch instructions would add to instruction decoding.)



1. More subroutines does not mean significantly more call nesting. It's nowhere near a linear relationship.
2. Putting parameters on the stack on the 6502 is somewhat pathological, at best. Parameters are almost invariably passed in other ways, unless you're using a language ported from a very different kind of system, like C, which is not at all suited to the 6502.


Yes, it was indeed stylized that way on the boot screen, as I said. Nowhere else, as far as I can tell.


All estimates are speculation, by definition; that doesn't automatically make them inaccurate. My complaint here was really that you come across as saying (to this native English speaker) that we don't have figures at all. If you're willing to update your article to say something like, "While no official sales figures were published by Apple, Tandy or IBM, we have estimates," we'll be on the same page.


Well, whether or not you consider MOS to have been "crushed," both development and manufacture of the 6502 continued, by several different companies, for decades, and it's being manufactured and sold even to this day, more than forty years later. That seems like a pretty unqualified success to me.


This is simply wrong. Research topic for you: find three more major companies that developed and manufactured processors based on the 6502 between 1984 and 2000. (Yes, they exist.)

---------

Let me mention, by the way, I'm not a 6502 fanboy. It's not my favourite processor by any means. But I have, in part through what I've learned in this forum, grown to respect the 6502 a lot more than I used to. It turns out that, if you look at it closely, there was some pretty damn good design work that went into that processor, and I now think that the longevity of the 6502 is solely due to mere nostalgia.

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Hmm... this exchange feels to me like it's headed in an unproductive direction. Any of us can reasonably expect to say what we believe - convincing others is a different case. Can we perhaps try not to point-counterpoint endlessly? Just let your statements stand for themselves and let the reader come to their own conclusion.

Thank you but IMHO it is a quite polite discussion.



A re-entrant routine for the 6502 or 6800 is something really contrived for me. However if you are ready for a contest just present your code at least for the 6800. IMHO the fact that 6800 was not used in any computer while the 6502 was so popular shows things quite well.

I can't imagine programming on the 6502 without the X register, I have written several quite large systems... IMHO any 6502 programmer can say you the same.


We have had a quite emotional discussion about this matter. I have to give you a link there - viewtopic.php?f=2&t=4220&p=46925&hilit=ugly+displacement#p46925 - it is also the code you are demanded. This discussion also has a picture of original MOS documentation about JMP (abs) execution phases.


It was a figurative phrase. Let's think. A solid company prepared a large number of computers to sell in the USA. They had to do much efforts for this. But they couldn't sell anything. Is it ok? The BBC Micro, Amstrad CPC 6128, and typical MSX 2 used disk drives.


The feature to be relocatable has some meaning together with module programming. Such programming was rather rare fore the 6502. The main feature of the 6502 was its speed. Why to use slow BRA when we have a faster JMP?


It is difficult to agree with this. There is always a way to send parameters with recursion support and without it. What is wrong with the first way? Some task, for example, the quick sort requires to use a stack for parameters.



Excuse me but almost all development for the 6502 was made by Bill Mensh. And this development was stopped on the 658126. IMHO one man is not enough to develop a processor. Why did nobody make the pipelining? Read the history of 6502, it is quite clear that several attempts to upgrade the 6502 were stopped.


Please provide me with more details. IMHO it was rather cosmetic changes, and controller adjustments.

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Ahem...

https://en.wikipedia.org/wiki/SWTPC

As far as I know those benchmarks was done in EDN which was independent of MOS Technology.



I have read you phrase again and I begin to think that you maybe just don't understand the subtle nature of this problem. I dare to recommend you to read the thread about it.



Thank you. However it is the KIM-1 class radio-amateur machine, a precious part of computer history, but I have been about famous brands like Apple, Atari, Commodore, Nintendo, ...

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Hmmm... let's see:

https://en.wikipedia.org/wiki/MEK6800D2

https://worldradiohistory.com/hd2/IDX-Site-Early-Radio/Archive-Wireless-World-IDX/70s/Wireless-World-1977-06-OCR-Page-0094.pdf

https://en.wikipedia.org/wiki/TRS-80_MC-10

https://en.wikipedia.org/wiki/Tektronix_4050

http://www.computercloset.org/SmokeSignalChieftain.htm

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The "second front page" is http://wilsonminesco.com/links.html .
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x86?  We ain't got no x86.  We don't NEED no stinking x86!

While I admire the author's goal to keep updating the article and also refine their grasp of the English language, I find the article highly subjective and full of biased language that diminishes the scholarly premise of the article:

Not a huge issue, but while Motorola's refusal to support the 6800 team in their quest to create a lower cost CPU is probably not directly known, one can easily conjecture some possible reasons.

• No need to do so until market demand necessitated it
• desire to not place too many resources in the pipeline until the market supported it
• issue with marketing a revised IC so soon after the initial into, etc.

More concerning, calling the 6800 a mediocre processor is useless without some actual data to back it up. The article claims MOS Tech specialists as noting 4X speeds, but no one would believe them (as others have pointed out). If the specialists were EDN, cite the source, so we can see what work load they were using. In general use, given the relative similarity of the ISA of both CPUs, I find it hard to believe either will be substantially better than the other. The 6800 will be better at handling tabular data greater than 1 page, given the 16 bit index register, while the 6502 will do better on loops and smaller tables due to the 2 index registers. Either way, calling a CPU mediocre without some actual data to back it up belongs in a puff piece, not a hard piece of journalism.

Not sure how Bill Mensch can be noted to have an ambiguous role concerning the 6502. Also, saying he made loug but empty statements is biased, unsubstantiated, and highly arguable. Bill noted in the recent VCF-PNW what he specifically did on the 6502 and the related ICs, and we know he got seed money from MOS/CSG to stand up WDC. I don't think WDC ever made the 6502, as Bill redid the design in CMOS and he specifically talked about working around the decimal mode patent when he did his design, so I highly doubt WDC would have sold NMOS 6502. Bill signlehandedly designed the 65C02 and C816 (and redesigned it when Apple demanded changes), so even if he does make loud statements, he has the clout to do so.

While the English construct is hard for me to understand (and I understand the author is not a native English speaker), the sentence about being microscopically improved and artificially partially incompatible makes no sense to me. I assume the microscopically improved is in relation to the small additional opcodes in the 'C02 design, but it would help if the author could explain what kinds of improvements should have been made. It seems the author is trying to compare the small improvements in the 6502 to the huge leaps the other firms had in 16 bit CPUs, but that's patently unfair. Even Motorola went back and improved the 6800 line with small changes (6801/03) and then some more changes (6809). The artificial partial incompatibility must relate to the specialized ROckwell instructions, but does the author not understand that when Rockwell comes to a small firm like WDC with lots of money to buy a design, but wants a few BIT instructions, you add the BIT instructions. That's not artificial, it's capitalism.

Also, in that paragraph, "These instructions became slower in a cycle, but at the same time they became more correct in some far-fetched academic sense". FIrst off, only the specific addressing mode with the bug was altered, so the instructions only lost a cycle when using that mode, while the article makes it sound like the entire lot of the instructions lost a cycle. Also, "more correct in some far-fetched academic sense" is blatant editorializing. It's now known the author doesn't care much for fixing the bug because few people would have seen or experienced it. But, there's no data to back up that people cared one way or the other. I also don't see how the code for the 65C02 would turn out to be "more cumbersome...". It's the same opcode, same function, no idea why it would change when compiled for two different '02 variants.

The paragraph about the companies second sourcing the 'C02 makes it appear they produced the NMOS 6502 at the same time, but that's incorrect. They were second sources for MOS NMOS 6502, and then second sourced the WDC 'C02 later.

CMOS is so much better than NMOS, so that statement is just false, even in the 80's. CMOS ran cooler, could push lines to either rail harder, and could be closed faster due to the inherent features of complementary MOS technology. But, that's not why an NMOS 65C02 was not made. It was not made because CSG was cheap, and would have had to retool to add those instructions into their layouts, which they had no reason to do so. And, Rockwell and SYNERTEK didn't own the mask IP for the NMOS 6502, so they could not just add the stuff to the existing masks. They'd have to relay out the CPU in NMOS, which can't be done from the CMOS masks. CMOS and NMOS are two different processes, and so the masks would be nontrivially different. Given that CSG was too cheap to redo the NMOS, CMOS is already there for Rockwell and SYNERTEK, there would be no incentive to make an NMOS version.

Interestingly, the paragraph on the 6509 skews the other way. The CSG 6509 way of accessing 1MB of RAM is so limited as to be almost unusable. I know, as I emulate the 6509 via the Nu6509 CPLD daughtercard that enables 6509 functionality using a 6502/65c02.

Commodore only did microscopic upgrades (need to find a better word than microscopic, it's not a great use here) because they were cheap and didn't see any value in R&D on the 6502. By '83 they were onto the 68K and the Amiga in the pipeline, so they were done with the 6502.

Saying Bill did not improve the NMOS 6502 seems highly editorial to me. He improved it by moving it to CMOS.

While the information on the C128 is not wrong, it suggests it's the CPU's fault. The problem with the C128 was not the CPU, but the fact that there was little demand for such a 65XX unit, and most developers could drive more margins by targeting the 64, which the C128 could also emulate.

I agree with cjs that the "unusually asymmetric" non orthogonality in the instruction set makes perfect sense when you know that the 6502 was designed to fit X on a wafer. You can tell from the design that at some point, the design was "chopped" to make it fit the die in such a way that X units would fit on a wafer. It's also the reason for the don't cares and such. The team left off as much as humanly possible to make it fit. That's how the price came down so much, as they could get more ICs per wafer, even with bad yields.

Hehe: "The 6502 can work in parallel with another device, for example another 6502. As far as I know, such dual-processor systems have never been produced, instead of the second processor a video controller was usually used, which shared memory with the 6502." Not true. All dual drive CBM drives are complete 6502 machines, with dual 6502s running inside, using shared memory. 4040, 8050, 8250. I think even the SFD1001 single drive uses 2 CPUs, but I might be wrong there.

"but clearly belated and with large architectural flaws". Again, realize that, while Mensch wanted to do it sooner, someone has to pay for it. When Apple came with money, Bill could do it. I don't think that's a flaw of the CPU, but of the market. Also, I know of no architectural flaws of the '816. It was designed to be an almost drop in replacement for the 6502 design. And, I disagree that "Bill Mensch didn’t even try to somehow improve his brainchild, do cycle optimization, replace the zero page addressing by extended one using the Z register (this was done in the 4510), add at least multiplication, etc. ". Many people know that Bill has a 32 bit version of the '02 designed, which was called Terbium. The market never asked for it, so he never produced it. The author seems to be under the delusion that companies will just create optimized versions of their designs when no one has asked for them, using personal cash to fund an effort which may never get used. Bill puts designs into production when people come with cash to buy them, not before. Same with Zilog and Intel. If we want to blame someone, blame the market, not Bill. I am sure he wanted to do the 32 bit '02, because he wrote the design up. But, a suitable customer never materialized.

The author isn't doing enough research. Considering: " However, even now (2019!) WDC for some reason, offers the 65816 only at the same 14 MHz. ", Bill has told many people, and it's documented. He notes they will run faster but he see no value in certifying them at the faster speeds (certifying requires testing and costs more money), and most folks either use the units at 8, 10, 20 MHz, or they use the soft cores, which the tool vendors (Xilinx/ Altera) would essentially certify the max speed during CPGA/ASIC layout.

I'll admit it's tough to slog through the article with the heavy editorial bias. If the author wants people to read the article, I think it'd be best to put the facts first in the main body of the article, and then put the editorialization at the end. Mingling the two just reduces the effectiveness of the article, in my opinion.

Jim

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The "second front page" is http://wilsonminesco.com/links.html .
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Jim:
> we know he got seed money from MOS/CSG to stand up WDC

That's interesting! If it's not new to me, then it's something I'd forgotten.

Thank you very much for reading and valuable comments. Indeed my material shows my point of view, it can't be completely free of gaps in my knowledge. I have really try to use only correct data but my other purpose is to make the article emotional, so it contains unproven assumptions (which can be true), information about contradictory claims, etc.



We have the MOS Tech specialists claim. Is there refutation of it? No. Instead of the refutation we have only some speculative phrases. Anyway I called the 6800 as mediocre not in absolute sense but in comparison with the 6502. I can give another example, IMHO the 8080 is mediocre in comparison with the Z80. I don't use word "mediocre" in the 6800 family article - https://litwr.livejournal.com/1396.html . I checked the 6800 ISA and it looks not so good as the 6502 ISA for me. I know the 6800 programming much worse than the 6502 so I am not completely sure in my points. Of course, for some tasks the 6800 should show good performance, for instance with signed arithmetic. We can try to make some research in this area.



I take this opportunity to express my respect to Bill Mensch and the results of his work. However you know that any results are imperfect and open for criticism. So the only way to evade it is to do nothing. IMHO it is good that Bill can get some critics sometimes. Thanks to your remark I changed a phrase in my article. Thank you very much. I have also changed several more phrases.





Sorry for my English. I am really not a native speaker. However it seems that you could understand my text almost well. I wrote about the 4510 (65CE02) several times, IMHO Commodore did several quite good improvements (a better instruction pipeline is among them) although they were rather too late. I also wrote about moving some zp memory to registers. So I have given some explanations of "what kinds of improvements should have been made". The 6801 has a lot of improvements: 16-bit instructions, multiplication, better execution timings, ... Nothing similar were present in the 65C02. The 6809 is rather a completely different CPU which only resembles the 6800 or 6801 - it is much more powerful.

"The artificial partial incompatibility" in my article relates to decimal instructions (we all know about Arkanoid bug) and JMP (ABS). Rockwell extensions are separate, they are incompatible only with the 65816.

Let me joke about your last phrase. A word capitalism was invented by Carl Marx, so when a man uses it I think "Wow! He is yet one more Marxist!"



I wrote "a number of changes were made, which in particular led to a change in the course of executing several instructions". IMHO it is definetely only about several instructions, namely decimal ones and JMP (ABS). Maybe the phrase about "far-fetched academic sense" is not the best but I don't how to express my thought that support of extra flags in the decimal mode was not worth incompatibility with timings.

About the JMP (ABS) we have MOS documentation which clearly shows cycle-by-cycle execution of this instruction... I have given the link to my code for cjs. The code actually more cumbersome for the 65C02. You can see the full code at https://github.com/litwr2/rosetta-pi-sp ... 502-div6.s

The use of new 65C02's instruction JMP (ABS,X) makes code much better than code with JMP (ABS). So I don't still find any reason to change JMP (ABS) in the 65C02.

There were no practical complains about JMP (ABS), all known complains were just theoretical. Anyway, it is documented and can't be bug.



"The 65C02 was licensed to many companies, in particular NCR, GTE, Rockwell, Synertek, and Sanyo. Synertek and Rockwell companies in addition to the CMOS 6502, also produced the NMOS 6502." - is this wrong?



Are you sure that CMOS of the early 80s was definitely better than HMOS-2? I have found an interesting cite from Motorola 68000 microprocessor Oral History:





Indeed, it was very primitive but IMHO it was better than bank switching used in many other 8-bit designs.



Thank you. I have replaced this word with word "tiny". Commodore eventually made the 65CE02 - quite a processor! However, Commodore rather buried all its fine initial projects.



Indeed he improved!



On the contrary, I wrote that there were problems to realize systems using the more fast 6502. As somebody had a strategy to slow down the 6502 progress. The poor design of the C128 confirms this idea.



I didn't write about this as about a drawback. It was rather a quirk, IMHO.



Thank you. I have to ponder about it.



I can repeat my point. One man is not enough to develop a processor. The 6502 team was disbanded. They were going to make a 16-bit processor in 1976. Bill could make it only in 1982. Bill several times told about fantastic designs but IMHO an engineer should have just shown them.

IMHO the main flaw of the 65816 is its special use of the first 64 KB of memory and not optimal work with addresses above 64KB. It also should have been much faster, IMHO. It was quite possible to speed up it later, IMHO.

I can't agree with you about the market role. The 6502 and most other processors were designed to form market, not to follow it.

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I don't think you succeeded. I can understand wanting to write an article that is not just statements of facts, but forces the reader to really think about the topic at hand. But, if you want to do that, you have to construct the sentences that are "emotional" in such a way so as to not immediately invoke the reader's guard. If you push the reader out of the reading "zone" into the defending "zone", you've lost the reader, in my opinion. Thus, I think you first have to get the reader heavily invested in the article, such that they will push towards the end. TO do that, you need to start with maximum facts, and minimal editorial, and then ramp one one as you ramp the other down through the course of the article. Also, you need to be more nuanced in your editorial. Saying Bill Mensch "played a rather ambiguous role" pushes people out of the article, because the groundwork has not been laid. If you had started by noting what Bill did do, showing the reader that you've indeed learned quite a bit about the man and his work, and seemingly building a platform for showing how important he is/was, THEN you can call out specific items (Bill was instrumental in the design of design of the NMOS 6502, but he was simply implementing the ideas given by Chuck Peddle. Once on his own at WDC, Bill hewed very close to the original 6502 design originated by Peddle, when there are ample opportunities to push the boundaries of the 65XX design... I think people would be more willing to accept the argument, even if they do not agree with it (I don't but I wouldn't dismiss it out of hand either).


A claim without a source is useless. Either cite the source in the article, as a footnote, or leave it off, or note the alleged nature of such a statement.


Weak. At some point, the evidence becomes too weak to present. Every time a CPU came out, there was a way to massage the numbers to make the new CPU look impressive, even when it was not. As such, people always look at such statements with skepticism, and they look at people who lift them and re-use them with the same skepticism. Essentially, the reader is thinking "Hmm, does the author even know how biased those statement are in general? I'm not sure they even understand the subject matter..." You NEVER want the reader to start questioning your grasp of the subject matter. You're the writer, it's your responsibility to build a convincing case, as you shape the message.


I don't think you'll find many people who agree. The Z80 is superior to the 8080, but that does not mean the 8080 is mediocre or inferior to the Z80 (For a non-English speaker, I know that sounds non orthogonal, but I can assure you the two words are not completely complementary.

The word "mediocre" is a loaded word, like "stupid", or "inept" or "useless". It is often used for effect, to amplify some perceived slight. Using it here implies you found the 6800 severely lacking. I think you may just be attaching not enough significance to the word usage. Consider "less optimal", "6502 is superior", or something like that. I think people will be willing to agree with you (6502 fans will be quick to agree the 6502 is "superior" to some other processor like the 6800, and some might even say it is superior to the 8080/Z80, even at 1MHz 6502 = 4MHz Z80). But, calling something "mediocre" is just asking for the fight. Case in point, the TMS9900 16 bit processor in the TI 99/4A is hardly a "mediocre" processor. But, the performance of the TI 99/4A suffered greatly due to system design constraints that strangled the poor processor's capabilities.


Bill felt the second index register was a good call, over the second accumulator. But, all in all, the two CPUs get about the same amount of work done per unit time, of a reasonable mix of work. Still, this is easy to test. The 6502 crowd can write some sample apps (sorting app or sieve or something else) and the 6800 crowd on the SWTPC or the MC10 could be asked to write the same thing. Results could then be compared. If you take out IO and such, the comparison would be pretty valid.


But, you made the accusation before laying the groundwork. And, even though you note the 4510 improvements, your statement was: "the 6502 was only microscopically improved and made artificially partially incompatible with itself." If we assume you bundle the 4510 into the 6502 line, your statement is "the 6502 line (including the 4510) was only microscopically...". If, we assume the 4510 is *NOT* included in the 6502 line, then your statement is "the 6502 line, until the 4510 was only microscopically...", which is better, but only if you've discussed the 4510 improvements before you make the statement. Without the introduction, the reader is left wondering what 4510 is and how it improved things. As well, the 4510 statement of improving things pokes a big hole in the master premise of you paragraph, which is that the 6502 never got the improvements it needed. Your point about the 4510 improvements is actually a good one, but I don't think that's noted in the article at all. It's one more folks might agree with.


Again, my point is that you explain the improvements later in the article, too late. But, if the improvements were made, then your statement that the 6502 was only microscopically improved is false, by your own admission. It was improved a lot, as you note. Pick a path here.



I'd call those out, to lay the ground work. If I was confused, so other are as well.

And, actually, we all don't know about these. The only reference I have on the arkanoid bug is around the NES version of Arkanoid, but that CPU has decimal mode disabled to avoid legal troubles, so I am not sure why the 6502 gets a ding if that's the reference. Help me out here.



My point is that most code does not use either decimal mode or JMP (ABS). So, if you ran an emulator with a hundred programs of various types and modified the emulator to count how many uses of ALU instructions with decimal versus not and how many JMP(ABS) versus JMP of any other type, I am confident you will find the ratios very small. Thus, the slowdown on decimal mode is minor, and the compatibility concern on JMP(ABS) is likewise minor. Again, these of things one can measure.

As for your thought, I think you're better off to go down the route I'm suggesting, noting that neitehr decimal mode nor JMP (ABS) is used often. Thus, fixing these bugs is of dubious value and introduced possible incompatibilities.


I still don't see how it is more cumbersome. The code you note uses the same assembly for 6502 and 65C02, thus it cannot be more cumbersome. It is, as you note, slower on the 65c02. I think you're saying that, to get back to the same speed, you need to do some conditional assembly, which creates some cumbersome effort. If so, I can partially understand. But, as I note, people use JMP (ABS) infrequently, in my opinion, but people use:

OP LEN CYC MODE FLAGS SYNTAX
-- --- --- ---- ----- ------
1E 3 6 a abs,X N.....Z. ASL $1234,X
5E 3 6 a abs,X N.....Z. LSR $1234,X
3E 3 6 a abs,X N.....Z. ROL $1234,X
7E 3 6 a abs,X N.....Z. ROR $1234,X

at least as often and potentially more frequently, and these are 1 cycle faster in the 65c02. So, all in, I think the 65c02 will save time, even with the 1 cycle penalty of the JMP (ABS).


Um, bugs can indeed be documented and still be bugs. All the CPUs I use have a long list of errata on them and people do indeed consider them bugs. Documenting something does not absolve it of guilt.

But, I see your point about the issue being theoretical. People were successfully working around the issue en-masse by then, so the value of fixing the bug was probably low.


I am not disagreeing with the statements you make, but the timing. Specifically: "Synertek and Rockwell companies in addition to the CMOS 6502, also produced the NMOS 6502". It makes it appear that these companies licenses and started producing the NMOS 6502 either at the same time or AFTER the CMOS 65C02, but that's incorrect. They started producing the NMOS in 1977 or so, when MOS needed second sources, and then they started producing the CMOS 65C02 in the early 1980s when WDC designed it. The sentence confuses the layman reader, who may not be aware that NMOS process predates the CMOS (or at least matured before the CMOS process).


Your statement was "Although in the early 80's CMOS technology had no obvious advantages over NMOS and was more expensive." You split out cost from capability. The oral history is talking about the economics of CMOS, and I am perfectly content to agree CMOS was more expensive than NMOS (or even HMOS-II) in the early 80's. But, you split the two out, and so I find issue with the "Although in the early 80's CMOS technology had no obvious advantages over NMOS..." portion. It had tons of obvious advantages (lower heat, faster speeds, better drive, etc.) than any NMOS process, HMOS or otherwise, could touch. If you want to simply state that CMOS was significantly more expensive, then I'd still quibble (because better products typically have a price premium), but you'd at least be correct in the statement.


Can't agree there. Sorry. I implement MMU designs on 8-bit 65XX/68XX systems, and a 4kB/8kB banking mechanism is orders of magnitude more useful than the brain dead mech in the 6509. But, at least on this point, our various positions are equal, in that it's your opinion against mine.


tiny is better. But, it's still an awfully loaded term. Minimal, or nominal, or half hearted I think would be better (and more nuanced). tiny and microscopic are boring words.



OK, then. acknowledge that in the article. Currently, the article still says "...he never tried to improve this processor himself." It's just wrong. Fagin improved the 8080 by designing the Z80. The same is true of Bill.


Yeah, I didn't wade into the BBC note you mention because I don't know much about it, but the above is just not correct on the C128. Sorry. CSG had faster 6502s, but making the interleaved dual processor design forced all parts to be twice as fast as normal, and CBM was not about to pay for sub 100nS DRAM to move the C128 to 3 or 4MHz (which demanded 6 or 8MHz capable DRAM), and they definitely could not switch from an interleaved memory design, as the 64 mode forced constraints. Commodore was cheap. It had nothing do with keeping the CPU speed down. It had to do with cost. And, I'm not sure what you mean about the poor C128 design. Bil Herd would challenge that notion a lot . I'm not a huge fan of the 128, but I don't see any glaring design issues. The Z80 looks shoehorned in because it was. Marketing demanded the unit be CP/M compatible, thinking the 64 mode could run the old C64 CP/M cart, but that cart was never robust, didn't work on newer 64s, and Bil got so frustrated trying to make it work he ended up just pushing the design into the C128 to check off the requirement. If there's a design issue, it'd be there.


Dunno, Bill did. He designed and developed the 65C816 himself. He's a pretty smart fellow, you should go chat with him.


Yeah, I saw you made that comment before. But, I looked at the ad, and I don't see any hint of 16 bits for a CPU. Can you point out where you see it? "The first of a low cost high performance microprocessor family" cannot be it, as that could mean so many other things.


Bill could only manufacture his design in 1982. Who knows when he created it. Your statement implies he only figured out how to do it in 1982, but there's no data to back that up.


Huh? I don't get this at all. Bill has grander plans, but he's not going to give away his secrets.


I think you are playing revisionist history. In 1982, The 8086 was 5MHz, but the CPU speed of a 8080-ish CPU is not completely equivalent to a 65/68XX CPU speed. 8080-family CPUs expected to run memory slower than the CPU speed. So, the core CPU could be made faster. You could argue the 65/68XX should have switched to that kind of design, but that probably would have broken lots of stuff. (and you already argued that fixing bugs that caused slowdowns and incompatibilities were useless, so you'd be even less enthused about having MOS or WDC decouple memory access from clock speed). So, even in 1982 or so, 10MHz (probably RAM speed of 2-3MHz) was pretty good, and 6502 was always the cheap CPU, not the speed demon. I think it was adequately fast at the time. Now, if you want to argue the CPU should have required a 48 pin DIP carrier and brought out the 16 bits of the data bus directly, and had an internal 16 bit ALU, there's probably more weight to that argument.

The 64kB direct page and the inability to work better with > 64kB memory are valid points, though I think they have to be viewed in the complex balance of existing code versus new functionality. At least it's something debatable.


The NMOS 6502 was, but not the CMOS 65C02. MOS had given up on the NMOS 6502, because they were now part of CSG, and CSG didn't care. Their fab was old and outdated, Commodore didn't want to sell ICs or CPUs, they saw more market in selling computers. Thus, the NMOS 6502 effectively died once the Peddle team disbanded. CSG wrung every ounce of value they could from the CPU, and was happy to take the royalties from the Rockwells and the SYNERTEKs of the marketplace, but no more R&D was done until 10 years later. If I remember correctly, the 65CE02 (of which the 4510 is a system on chip design that includes the 65ce02 and an MMU and some CIAs) was a further refinement of the 65C02 design by WDC, which CSG had access to due to a cross licensing agreement with WDC. The entire 64DX project looked like a last ditch effort to pick up more of the low end of the market, like a ZX-81 for the late 1980's, early 1990s. I further suspect that Bowen and others who worked on the 64DX brought the 65ce02 in the back door by suggesting it would be useful for Amiga peripherals (like the A2232 serial card it was eventually used in), but perhaps the team got the go-ahead on their own to update the CPU. In any event, it was too late, and half hearted at best (your argument about speeds is absolutely relevant here, since the CPU only runs at 4MHz or something, and 4MHz in 1989 or so was anemic, even for 68XX/65XX designs).

Bill, on the other hand, did not have the muscle to form a market. He was simply too small. He had to wait until the folks wanted a 65XX compatible CPU in CMOS, because that's all he had to offer. Maybe you think less of Bill because he did not go champion the 65C816 or the 65C832 or the other designs, but I don't think he ever planned to do that. He simply wanted to further the 6502, fix the bugs, and continue it's evolution. Even today, when soft cores mean anyone can push out a new processor family, WDC does not do so. They offer 65XX compatible ICs and soft cores.

Jim

I'll have to second this. While the Y register seems more immediately useful, the X register is important as well. A page zero argument stack indexed with the X register is for me the key to writing reentrant code on the 6502!

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?