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PostPosted: Thu Sep 27, 2018 4:18 pm 
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I was reading over the preliminary data sheet for the W65C832 that WDC put out in 1990 and I found it to be very interesting.

https://downloads.reactivemicro.com/Ele ... 20v2.0.pdf

According to the register diagrams it looks like only the Accumulator and Index registers were extended to 32-bit, with the PC and SP remaining as 16-bit registers with 8-bit bank registers to extend them to 24-bits.

Clearly this was done for compatibility reasons so that old code could run without modification, but I find it very confusing because the same datasheet references addressing more than 24-bits in the second introductory paragraph. I am not sure how you would address more than 16MB if the PC and SP were still in a 16+8 configuration.

It seems like this data sheet was literally thrown together at the last minute, it was obtained by someone writing WDC pretending to be a big manufacturer looking for a 32-bit 6502, so it is possible the register diagrams are just wrong and in 32-bit mode the PC and SP would also be 32-bits.

It is also interesting that WDC again was targeting a 40 pin design with an 8 pin databus. Overall performance would have been about the same as the 65c816 except on 32-bit maths.

I do not believe this would have been a successful product.


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PostPosted: Thu Sep 27, 2018 6:45 pm 
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It'd be kind of cool if it multiplexed A15-A8 with D15-D8 and A7-A0 with A31-A25. Full 32 bit address 16 bit data in PDIP-40!


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PostPosted: Fri Sep 28, 2018 1:03 am 
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shoggoth wrote:
It'd be kind of cool if it multiplexed A15-A8 with D15-D8 and A7-A0 with A31-A25. Full 32 bit address 16 bit data in PDIP-40!


Probably doable at the low clock speeds at which WDC processors generally ran.


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PostPosted: Fri Sep 28, 2018 8:42 am 
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(Hi shoggoth, and welcome! A 32-bit address bus in a 40DIP would indeed be quiet something!)

I agree that this datasheet, while very interesting, looks very much like a rush job, and isn't entirely consistent.

Interesting possibility that the '832 might have only been an update to the arithmetic and register width, not the address width. As you say, rpiguy2, that would help 32 bit operations, so operations on integers and on pointers, both the speed and the code density, but with only quite a minor change to the architecture. More like an '816plus than an '832. WDC had (and have) such limited resources that small tweaks which add a reasonable amount of value must be very attractive to them.

And 16Mbyte of addressable memory, at that time, would have seemed plenty. AFAICT, the 68000 had the same restriction, and the ARM1 went only to 26 bits.

It might be worth reading over some previous threads too:
Unfortunately I think there are some dead links within.


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PostPosted: Sat Sep 29, 2018 2:16 pm 
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Joined: Mon Sep 14, 2015 8:50 pm
Posts: 110
Location: Virginia USA
Here are some cleaner datasheets for the w65c832 and w65c365

Attachment:
DSAP0032005.pdf [2.07 MiB]
Downloaded 179 times

Attachment:
DSAIHSC00061261.pdf [3.17 MiB]
Downloaded 159 times


There is one third party source for soft core 65832 available via license:
http://vlsi-concepts.com/v65C32.html

Cheers!
Andy


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PostPosted: Sat Sep 29, 2018 2:23 pm 
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Location: North-Germany
handyandy wrote:
Here are some cleaner datasheets for the w65c832 and w65c365

Attachment:
DSAP0032005.pdf

Attachment:
DSAIHSC00061261.pdf


There is one third party source for soft core 65832 available via license:
http://vlsi-concepts.com/v65C32.html

Cheers!
Andy

Thanks for the cleaner sheets and that link - interesting :)


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