I've seen designs that fully qualify a memory read/write into two separate pins (/MRD and /MWR).

For example, Daryl's SBC 2.5 does this using the R/W and CLK2 inputs. That way, you avoid writing to RAM while O2 is low.

But I was wondering...if using a CPLD for memory decoding, would you still recommend putting read/write into two separate pins? Or, would making a "virtual" R/W pin be good enough?

I was thinking the virtual R/W pin could act like the normal R/W but this one would be controlled by the CPLD. In fact, could you not use a global clock for PH2 and another global clock for R/W? That way, the CPLD would only need one I/O pin for the new R/W.

Thanks for any tips.

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Cat; the other white meat.

You could setup your CPLD to do the address decoding, but qualify the ~CE outputs by PHI2. Then the inputs on your RAM (etc) could be arranged ~RE -> Ground, ~WE -> R/~W, assuming that your RAM chip's ~WE overrides ~RE, which in my experience they usually do. This would indeed save you a three pins on your CPLD - since you wouldn't need an R/~W in, nor ~RE & ~WE out.

The main downside is that most RAMs and ROMs i've seen take less time for their output to settle from ~RE/~WE than they do from ~C,E so, depending on your clock speed, it can be advantageous to allow ~CE to go low whilst PHI2 is still low, so that the RAM has maximum time to respond to the ~CE. This means your minimum access time becomes the RE/WE-to-valid time rather than the CE-to-valid time.

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Want to design a PCB for your project? I strongly recommend KiCad. Its free, its multiplatform, and its easy to learn!
Also, I maintain KiCad libraries of Retro Computing and Arduino components you might find useful.

I used an Atmel ATF22V10CQZ as a single glue logic chip in my last SBC project. It handled address decoding for RAM, EEPROM and 5- 32-byte wide I/O selects... plus qualified /MRD and /MWR signals based on the CPU CLK and R/W as inputs. I used a NXP UART for console/timer, which has separate /RD and /WR signals, so separate signals are requred. I used the same (signals) for RAM, EEPROM (with a write protect jumper) and the UART. I also have these signals on the expansion bus connector for additional I/O devices.

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Regards, KM
https://github.com/floobydust

Qualifying /CE with Ø2 is not a recommended practice. For best performance, reads and writes should be the only thing qualified with Ø2.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

I did explain that point in the rest of my post, nevertheless it is possible.

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Want to design a PCB for your project? I strongly recommend KiCad. Its free, its multiplatform, and its easy to learn!
Also, I maintain KiCad libraries of Retro Computing and Arduino components you might find useful.

Doing a swan dive off a high voltage tower is possible as well, and also not recommended.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!