It's quite a complicated area. The only official notation is what's drawn on the 6502 schematics, which are not public. Donald Hanson's block diagram is drawn up as his best understanding, at the time, of what was on the schematic. The notations in visual6502 are not precisely the same, because they were made up before we saw the schematic. Indeed, they are a combination of our own conclusions, and notations by Balazs, and notations by other 6502 investigators.
Within visula6502, we find this:
Code:
if(busname=='tcstate')
return ['clock1','clock2','t2','t3','t4','t5'].map(busToHex).join("");
which tells you the 6 signal names used to construct tcstate. We also find this:
Code:
// The 6502 TCState is almost but not quite an inverted one-hot shift register
function listActiveTCStates() {
var s=[];
if(!isNodeHigh(nodenames['clock1'])) s.push("T0");
if(!isNodeHigh(nodenames['clock2'])) s.push("T1");
if(!isNodeHigh(nodenames['t2'])) s.push("T2");
if(!isNodeHigh(nodenames['t3'])) s.push("T3");
if(!isNodeHigh(nodenames['t4'])) s.push("T4");
if(!isNodeHigh(nodenames['t5'])) s.push("T5");
return s.join("+");
}
Within the 6502 schematic we see six named control signals as three of the rows of the PLA, all of which have an overbar to signify inversion: T5, T4, T3, T2 at the top of the PLA, and T1, T0 at the bottom. Looking at these horizontal poly lines in visual6502, we see the expected names as seen in the code blocks above.
So the mapping of T0 to T5 is clear, as signal names. As state names it's another question. For example
T5 seems to be stored in node 18
T4 in 1606
T3 in 644
T2 in 1360
These nodes are not named in visual6502, and I might have made a mistake just now in tracing back.
clock1
clock2
are driven from rather more complicated circuits, I don't want to trace those back at this time.
Note that the SYNC pin is labelled on the schematic as T1. In visual6502, it's driven by node 862. That node in the schematic is labelled T1.