Donald F. Hanson drew his 6502 diagram. A block of timing generation logic has 8 registers: T0, T1, T1X, T2, T3, T4, T5, and T6. This Visual 6502 shows that timing generation logic only has 7 registers, but not 8 registers. I have no idea where T1X comes from or it does not have storage. Perhaps, T0 and T1X are tied into one gate logic. T0 has storage. After T0 goes high and then low, the data state is transferred from T0's storage to T1X's storage and then inverted for T1X output into programmable array logic.

This looks like that node 1533 is T0's storage and node 554 is considered to be T1X's storage, but it is actually to be ready's storage. Please confirm if my comment is correct.

Take care,
Bryan

It's quite a complicated area. The only official notation is what's drawn on the 6502 schematics, which are not public. Donald Hanson's block diagram is drawn up as his best understanding, at the time, of what was on the schematic. The notations in visual6502 are not precisely the same, because they were made up before we saw the schematic. Indeed, they are a combination of our own conclusions, and notations by Balazs, and notations by other 6502 investigators.

Within visula6502, we find this:
which tells you the 6 signal names used to construct tcstate. We also find this:

Within the 6502 schematic we see six named control signals as three of the rows of the PLA, all of which have an overbar to signify inversion: T5, T4, T3, T2 at the top of the PLA, and T1, T0 at the bottom. Looking at these horizontal poly lines in visual6502, we see the expected names as seen in the code blocks above.

So the mapping of T0 to T5 is clear, as signal names. As state names it's another question. For example
T5 seems to be stored in node 18
T4 in 1606
T3 in 644
T2 in 1360
These nodes are not named in visual6502, and I might have made a mistake just now in tracing back.
clock1
clock2
are driven from rather more complicated circuits, I don't want to trace those back at this time.

Note that the SYNC pin is labelled on the schematic as T1. In visual6502, it's driven by node 862. That node in the schematic is labelled T1.

Your assumption is to be correct as I already drew my own timing generation logic schematic. The timing generation logic has seven registers, but you mentioned six registers. T1 is not part of clock1 and clock2 because it does not fire signal into programmable array logic. The node 646 is T0 and node 1533 is T1X. An inverted T0 as clock1 is node 17 and node 1536. An inverted T1X as clock2 is node 156.

According to my conclusion, node 1533 is supposed to be T0 as storage, but I decide to name T0 + T1X on node 1533.

The timing generation logic is divided into four blocks: T0 to T1X, T2 to T5, T6, and T1. T6's storage is on node 698 and T1's storage is on node 666. Both T1 and T6 are not part of programmable array logic. T6 is used for hardware / software interrupt handler. T1 is to delay one or two clock cycles while branch is in the process before next instruction begins.

Take care,
Bryan