BitWise wrote:
Setting a bit in PCS7 enables the associated chip select so when PCS7<3> is 1 the external RAM is enabled as it is the in default $FB setting.
So after going through the documention again -
http://www.westerndesigncenter.com/wdc/ ... 5c265s.pdf on page 37/38 - let me walk through this to see if I understand it:
The chip selection is handled by Port 7, which is output only. Since it is not a bi-directional register, it doesn't have a data direction register (PDD) like the other ports, but (as the schematic on page 50 shows), an "enable register" called the Chip Select Register (PCS7 at 00:DF27). It also has a Data Register like the other ports (PD7 at 00:DF23).
Based on section 2.9.2 on page 37 and section 2.14 on page 38, a 0 bit in PCS7 means that the value in the Data Register will be output on the chip select line. For example, if PCS7<3> is "0", whatever is PD7<3> is what will be on the pin. In other words, in this mode, it's a simple output port for its data register. If there is a "1" in the PCS7, however, we turn that pin into a chip select line. At reset, the documentation claims, PCS7 is all "0" and PD7 is all "1".
However, after boot, I get $FB (%1111 1011) in the PCS7 at 00:DF27, which means that everything except bit 2 is set up as a chip select line. The data register for port 7 at 00:DF23 gives me $04 (%0000 0100). We only care about bit 2, because everything else is in the data register is blocked by the 1s in PCS. That 1 in bit 2 is what we see on the pin, and because we're "active low", it's making sure that we don't select something. And
that is to make sure we use the on-chip "stuff" (as the Monitor code listing puts it) such as the on-chip ROM, on-chip interrupt vectors, etc.
Does that sound about right?
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