The label of phi2 in the 6502 MPU's pinout is actually clk0. It is supposed to be inverted phi2. If the line is pulled low, then cp1 (710) goes high and cclk (943) goes low. To complete one clock cycle, cp1 (710) goes low and cclk (943) goes high during phi2 is high before cp1 (710) goes high and cclk (943) goes low during phi2 is low.

The inverted reset line is pulled low while reset process needs more time in order to charge the capicator during cp1 (710) before the pass gate is activated and capicator is discharged during cclk (943) so that reset's data becomes stable and is stored in D flip-flop.

I want to know if anyone is going to agree that clk0 is labeled as inverted phi2 because it is easier for us to observe that cp1 (710) does first and then cclk (943) does second in one complete clock cycle.

Bryan

Pin 37 of a 6502 is the clock input, often labelled Phi0. In visual6502, this node is called clk0.

From clk0, two non-overlapping clocks are produced on-chip, driven around the chip and also driven off-chip.

In visual6502, the two on-chip clocks are called cclk (four inverting logic gates later than clk0, therefore approximately the same phase) and cp1 (five inverting gates later than clk0, therefore approximately the opposite phase.)

Pin 39 of a 6502 is a clock output, often labelled Phi2. In visual6502, this node is called clk2out.

Pin 3 of a 6502 is a clock output, often labelled Phi1. In visual6502, this node is called clk1out.

For most purposes, on the outside of the 6502, we concentrate on the role of Phi2, and we consider Phi0 to be the same phase. Likewise, I think of cclk as being phi2, and cp1 as being phi1, although in fact there is a small delay or phase shift.