I am just about to do the routing for a PCB construction my first 65C02 SBC (using OSH Park which happens to be here in Portland). I was inspired by a few of the SBCs here on 6502.org, in particular the work by phvic and the ERIC-1 (viewtopic.php?f=12&t=3103) and Michael's mini PCB design (viewtopic.php?f=1&t=2854).

My design is somewhat similar to those designs in that I am using a PIC microcontroller as both the 'bootloader' as well as the 'interface' device.

In my particular case I am planning of the following:

(1) The PIC will generate the primary clock and reset inputs for the 65C02. This could run the 65C02 at up to 10MHz, or as slow as DC. Since I am using a 65C02 the PIC can also use the BE pin to disable the CPU outputs.
(2) The 65C02 will have 32K of SRAM at 0x0000-0x7FFF, and 16K of SRAM (simulating ROM) at 0xC000-0xFFFF.
(3) For diagnostic purposes I have two 7 segment displays off of a 3:8 decoder at 0x8800 and 0x9000.
(4) At start up, the PIC will put the correct code into the upper SRAM chip, then fire up the 65C02.
(5) For communication from/to the 65C02 and the PIC:
The 65C02 will write to a predefined memory buffer in the upper SRAM, and let the PIC know there is data there by writing 0x8000 (which will trigger the 3:8 decoder output to the PIC Interrupt pin)
The PIC will write to a memory segment in the upper SRAM when data needs to be returned to the PIC, and let the 65C02 know using the 65C02 interrupt pin.

By using the 'shared' SRAM for communication, I can have buffered data in both directions, multiple command sets, etc.. Easy to expand in software.

For the PIC to be able to read or write to the upper and lower SRAM, it will need to pause the 65C02 CPU and use the BE pin to tri-state the bus lines from the 65C02. You can see the AND gates right before the MEM /WE and MEM /OE pins going to the SRAMs. Those AND gates allow the PIC to either control those lines, or pass through what the 65C02 is doing.

Unlike a few of the other designs, I am only using 8 digital IO lines on the PIC for address and data, so I added 3 latch/buffers. This gives me more lines on the PIC for other devices. I have two serial ports, plus two SPI ports pulled out. I suspect I will use the SPI ports for keyboard and display connections.

The schematic mentions a 'MicroFTX', which is a small board that has the surface mount serial to USB chip plus the USB connection already mounted. They can be found here: http://jim.sh/ftx/

Here is a PNG of the schematic:



And here is a link to a PDF of said schematic:

http://www.sponaugle.com/post/65C02SBCSchematic.pdf

As well as the DIPTrace schematic:

http://www.sponaugle.com/post/6502SBCMainBoard_V0.12.dch

I still need to add decoupling caps, and power and ground to some of the ICs. Once that is done, I'll quickly do the routing and get some boards made.

I'll post up the fully routed board, all files need to get PCBs made, complete parts manifest, and all of the source code and compiled code to get it working.

I'm looking for any comments/ridicule/that wont works/etc! Anything look wonky?


Cheers,

Jeff Sponaugle

Based on some feedback on another thread (viewtopic.php?f=1&t=3185&p=36447#p36447).. I have made a few changes to the design. I changed the memory /OE and /WR logic to a simpler design, and removed the use of the 65C02 PHI2 output (instead opting to use the input clock signal). The picture above is already updated, as are the PDF and Diptrace files.

Jeff

Hi Jeff,

Have you considered using a single RAM chip (64K or 128K)?

Good luck on your project.

Cheerful regards, Mike

Looking in more detail now. I see that Alliance has a 64kx8 part: AS6C1008-55PCN. That looks like it would do the job. I like your idea of using the chip selects to take out a 16k mid section of the memory. I'll drop this into my schematic and see how it looks!

Jeff

The AS6C1008-55PCN is 128KB.

There's also the AS6C4008-55PCN which has the same number of pins but has a whopping 512 kilobytes. And it only costs $2 more than the other one

And the pinouts are compatible: if you design for the AS6C4008, you can plug in an AS6C1008 in the same socket, or a 62256 (32K) or a 62128 (16K) or even smaller.

(As I mentioned elsewhere, 64KB chips are surprisingly hard to find, though you can probably still get the 62512 from eBay as New Old Stock)

===Jac

I always think it's a bit odd that 8-bit CPUs can address 64K but RAM chips come in 32K and 128K. I guess it's just the geek verson of canned hot dogs and their accompanying buns.

_________________
Andrew Jacobs
6502 & PIC Stuff - http://www.obelisk.me.uk/
Cross-Platform 6502/65C02/65816 Macro Assembler - http://www.obelisk.me.uk/dev65/
Open Source Projects - https://github.com/andrew-jacobs

Jeff,

I would consider to use a MCP23S17 16-bit IO expander for the address bus. That would make it possible to read the addresses generated by the 65C02 when doing single cycles via the clock generated by the PIC. Let's say for debugging purposes. And you could probably even avoid the 74xx245 bidirectional buffer for the data bus and connect it directly to the PIC.

Peter

posted by mistake