So, I've read many times that the Apple II's video generation hardware read from video RAM during the first half of the 1MHz cycle and the CPU used the RAM during the second half.

However, I'm having a difficult time understand how that worked while the CPU needed to write to RAM.

According the primer:

http://wilsonminesco.com/6502primer/addr_decoding.html



OK, so that means RAM is to be written while the Φ2 is HIGH. Right?

So how would that work? If the CPU was writing to address X but the video generation was reading from address Y, how could they both do that during the first half of Φ2?

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Cat; the other white meat.

Presumably, the CPU does its access when Φ2 is high, and the video circuit does so when Φ2 is low. If the video access occurs in the "first half", that must be the low half.

Also note that, since the video circuit doesn't ever write, there doesn't need to be any fancy handling for RMW instructions, unlike the possible situation with a shared-memory multiprocessor setup.

This rule of thumb is a simplification - a useful simplification. The danger that's being avoided by this rule is having a chip write-enabled when it's not safe to write - unsafe either because the chip shouldn't be enabled at all, or because the address lines are not stable and so the write might be directed to the wrong address within the chip.

So, by convention, many simple 6502 circuit designs use the clock to distinguish between the first part of the cycle, when address lines are still changing, and the latter part of the cycle, when they are steady. Few chips actually care about the clock - the clock is a convenient way to measure enough time that the address lines are stable. There are one or two chips which do care - as ever, the datasheets and an accurate timing diagram will help.

But other designs are possible: designs like the Oric which divide a clock cycle into several parts using a higher-frequency clock and do several things within one cycle (three things, IIRC) and designs like Acorn's Atom and, probably, the Apple II, which will carefully juggle propagation delays to allow for a video system access during phi1 and a CPU access during phi2. (In Acorn's case, this means two accesses per cycle at 2MHz which is twice as fast as Apple's constraint.)

See also Dr J's timing diagrams here, which are discussed here.

The Commodore 8032 goes even further: it not only switches the video RAM between two address buses and data buses, it's also configured in a way such that the video hardware sees the video RAM as 1024 addresses with 16 bits of data while the CPU sees 2K of 8 bits.

Ruud Baltissen's redrawn 8032 schematic at http://www.baltissen.org/images/8032.png (*) makes it pretty easy to see how this works: The video RAM chips (4 chips in the center of the drawing) have their address buses connected to two 74LS157 which are directly controlled by Phi2. The data bus of the RAM chips is connected to the CPU via 74244's on the left, and to the video hardware via two 74LS373 octal latches on the right.

The system uses a 16MHz clock that's converted to several phases of 1MHz by using a shift register if I recall correctly, and the data bus buffers and latches are controlled by the R/!W line, some of those clock phases and an address decoder. Because there are two 74LS373's, two bytes are decoded at the same time; one from an even address in 6502 space and one from an odd address in 6502 space. They are used by the 6545 CRT controller to generate an address in to the character ROM; the CRTC generates characters at double speed (16MHz pixel clock, 8 pixels per character, 2 million characters per second) so during one CPU clock cycle it generates the pixels for two screen characters: one character at an even address and one character at an odd address in 6502 address space.

It's a clever way to make an 80x25 screen for a 1MHz machine with a 2MHz character clock.

===Jac

(*) Ruud's schematic may have one or two small mistakes but it's otherwise very good