So, I wanted to beef up the memory on my Sym-1 to 32 K using a D43256B 32K x 8 bit static RAM chip. I built a little daughter board to go on the "E" connector, ho0oked it up, and verified that the monitor worked. Well, it worked fine from the keypad, but the RS232 connection will not respond. Pulling the 32K board and replacing the 2114 chips on the main board and the serial connection works fine.

Okay. Next I pulled the 2114s again, put on the 32K board and pecked a little program into the keypad to test the memory, and everything works out. The memory test program just goes to each location writes and verifies an number of patterns then moves on to the next. If it finds a bad location it turns on an LED connected to one of the I/O pins. No problems. The memory checks out just fine and the memory test has been looping for 3 days.

Any ideas why 32K of RAM would prevent the RS232 function from working?

Any help would be appreciated.

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Bill

On the run here, but I seem to recall that the Application (not Expansion) connector on the SYM has the same signals as on the KIM-1. If so, there's a decode enable that needs to be tied low if there's NOT any expansion. Seems like it could affect I/O, and maybe have a bearing on your problem.

The KIM-1 User Manual is here. On page 26 it shows Decode Enable on pin A-K.

Hth...

Jeff

ETA: the SYM manual is here. On pg 4-8 it shows RS232 connections coming from U27 -- a 6532. So, is this chip affected by your expansion? Still checking...

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
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Curiouser and curiouser! Sorry about the superficial response above -- this is stranger than I supposed. (And the SYM has no Decode Enable on pin A-K.)

I thought this has to do with some sort of decoding fault causing simultaneous activation of U27 (the 6532) and your new RAM chip -- even though that's seemingly contradicted by the fact the keypad is still working. (The keypad and the RS232 both use U27. You'd figure they'd both work or neither of 'em would work!) Still, I've seen contradictory situations before, and the (unlikely) simultaneous activation theory is still the most plausible I can come up with (except maybe a power supply issue). [Edit: or an address-line short -- see below]

The manual makes it hard to see where U27's chip-select originates, but I think it's one of the signals called /A0 and /A8 on page 4-31, and called /AA0 and /AA8 on page 4-27. IOW pin 5 or 6 of decoder U10 drives U27's chip select.

How about a little test program with a loop that reads (or writes) RS232 IO in U27 then a congruent location in the space occupied by your new RAM? An oscilloscope would reveal whether there's any simultaneous activation.

J.

ps- a short on one of the address lines of the new RAM chip, or its board, is actually a likelier explanation for the symptoms you're seeing. Your memory-test program might overlook this, since it tests each location in isolation from the others. So it's still oscilloscope time, IMO!

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
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Thanks Jeff,

Yeah, I think a little quality time with the scope might be beneficial.

_________________
Bill

Okay, I got this figured out.

The problem still seems strange to me, but the memory board is now working.

To make a long story short, I had originally used the phi2 gated R/W that was used to access the RAM on the SYM-1. For some inexplicable reason, this did not work with the 32K x 8 chip I'm using when I tried using the RS232 terminal. Worked fine with the keypad. What does work is the normal R/W signal. I have no idea why this should work.

The only thing I can think of is the 43256 is a 70ns device and the phi2 gated R/W goes through 4 LS series gates/inverters and the result created a timing issue in the system. But why it's only seen when the RS232 is used is beyond me. The logic on the system is pretty straight forward and scouring through the monitor routines WRT RS232 I/O revealed nothing.

I'm happy it's working, but I hate not knowing why!

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Bill

OK, from the perspective of the RAM chip, during write cycles /WE made a high-to-low transition partway into the Phase2-high period. That raises the question, are /OE and /CE low at that time? What's the source of those signals?

If /OE and /CE are low, then /WE subsequently transits from high to low, you have the beginning of a Read access -- subsequently changing to a Write access! And the Read access creates bus contention on the data bus.

I'm happy too -- and the point I raised doesn't fully answer the question "why?" But 10 or 20 ns of bus contention could result in marginal operation -- and that could manifest in strange ways. Just thinking out loud, here...

J

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

and depending on the board layout, inductance in the power and ground connections to the IC, combined with the high current spikes resulting from the contention, may drop enough voltage to even shift the input thresholds enough to suddenly make the perceived address different. Nasty stuff, that inductance!

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The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

/OE is tied to ground and /CE is tied to A15. I did it this way because when A15 is low on the SYM-1, no other devices are selected and when /CE is high on the 43256, the output is in a HI-Z state. The CPU should not assert the data bus until about 150ns after the transition low on the phi2 gated /WE so there should be no contention, right?

_________________
Bill

I'm not sure where the 150ns figure comes from, but the CPU will assert the data bus very shortly after Phase2 goes high -- and this is independent of any external gating. (To know the pertinent CPU bus-enable spec, we'd need to know what version of 6502 you have -- and even the spec won't tell the whole story.) What 's the clock rate, BTW?

If you want to test the contention theory, remove the ground on /OE and instead drive it with an inverted copy of Phase2. ( Edit: better yet, take whatever's fed to /OE on the original 2114 RAMs -- which is probably the NAND of R/W & Phase2.) I think you'll find that will work -- regardless of which of the two /WE sources you choose.

cheers,
Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

It just a Synertk SY6502 in NMOS. The 150ns comes from Tmds (data setup time)


1 mHz


Thought of that. I might give it a try just to get an answer. There is a /phi2 signal available on the expansion connector.


As you state, the original RAM was just 2114s. They have no separate output enable just /CE and /WE

_________________
Bill

Drat! I used to know that!
Sorry the for mixed messages in my (edited) post. Unqualified /phi2 straight from the expansion connector might work or might not. You said /WE arrives after several gate delays, so if you use unqualified /phi2 then it should have several gate delays to match or exceed the delay feeding /WE. But I guess there's at least one inverter delay on the /phi2 signal at the expansion connector, and that inverter delay might bring you into the zone that manages to work -- despite the inadvisability of using unqualified /phi2 in the first place.

Your solution of feeding the CPU's R/W straight to the RAM is okay. [Edit: no, can't believe I said that! Better to go with the original choice -- phi2 gated R/W that was used to access the RAM on the SYM-1.] But in context of the previous setup, the contention won't be properly be eliminated until write cycles guarantee /OE to be high during the entire Phase2-high time -- as with the NAND I mentioned. Unqualified /phi2 from the expansion connector might work -- especially if it's additionally delayed by a couple of inverter sections. (But that trick won't win any prizes for engineering!)

-- Jeff

[Edit -- booboo re /WE]

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

On the expansion connector there is a /phi with a single gate delay and R/W with 2 gate delays.

I just put a couple of 2 position jumper blocks on the board so that I can choose the following:

J1 - phi2 gated W/R or W/R to /WE

J2 - /phi2 or GND to /OE

I see no bus contention on the data bus with a scope in any configuration, however now even the original configuration works fine! Go figure?!?!

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Bill

You've strayed into the realm of Stuff That Shouldn't Work But Does. It's a not a comfortable place!

To clearly see contention on the scope you'd need a tight loop executing writes to the RAM. And -- -- the data being written to the RAM location would have to oppose (differ from) that which already resides in the location.

The fault we're looking for is an access which, from the RAM's POV, begins as a read -- contrary to intention. Later in the cycle it resolves to the write we wanted & expected.

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

I ran the tight loop which ran at about 100kHz, but could see no contention with any configuration. I guess that D43256, being a fairly modern device does the whole read/write transition properly.

In nay case, I found the fault! U2 (a 7404) was responsible for many of the buffered R/W and phi2 signals, but was barley getting to 2.7V on the high side and some of the subsequent signals looked a bit flaky. I replaced it with a 74ACT04 and the signals from it go rail to rail. Now everything looks honky dory!

Thanks for your help Jeff.

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Bill

Huh. You're welcome, and I'm glad for your success, but honestly I don't get the feeling this problem is truly resolved -- at least not based simply on replacing that inverter. TTL logic levels define anything above 2 volts as a valid high, so the 2.7 volts you observed is satisfactory -- not an indication that the inverter is defective. No doubt the 74ACT04 produces nice rail to rail waveforms, but that's unnecessary as long as highs are >2V and all chips fed by the inverter have TTL-compatible inputs. The RAM does, as does the CPU and chips from logic families such as 74, 74LS, and 74HCT or 74ACT.

Anyway, best of luck -- and if you get into any interesting experiments with your SYM, I hope you'll share them with us!

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html