I know that the power supply can provide positive voltage and zero voltage (ground) to 6502 microprocessor. Can negative voltage be provided, too? If negative voltage is used, then all PNP transistors must be used. In other words, the negative voltage can be applied to some NPN transistor’s gate terminal such as depletion NPN transistor.

For example, bit 0 of accumulator register has three enhancement transistors and two depletion transistors. The positive voltage is provided to t2654’s gate terminal before t2654 is turned on. The current from power’s drain terminal flows through the depletion transistor’s n-type channel and t2654’s n-type channel toward the ground’s source terminal on node 5 very rapidly while reducing the current toward t3065’s gate terminal before t3065 is turned off. The current from power’s drain terminal flows through the depletion transistor’s n-type channel toward t1507’s drain terminal on node 146.

Both t2654’s gate terminal and t3065’s gate terminal have capacitor. The t2654’s capacitor on gate terminal is fully charged and t3065’s capacitor on gate terminal is completely discharged because the current comes out of t3065’s capacitor on gate terminal toward the ground’s source terminal through t2654’s n-type channel.

If the feedback from clock 0 pinout is stopped, how long will the charge remain in the capacitor until it decay? Where will the charge from the capacitor flow while power’s drain terminal and ground’s source terminal are disconnected?

This explains why the depletion transistor is always turned on so that either positive voltage or zero voltage is applied to the gate terminal is ignored by the depletion transistor. The depletion transistor will be turned off unless negative voltage is applied, but there is no negative voltage across 6502 microprocessor’s circuit.

Please clarify and explain little more if I understand correctly since I have been studying and researching MOSFET transistors.

Bryan

Quick answers to a couple of points:
- No 6502 uses a negative voltage, either from the power supply or created on-chip by a back-bias generator, although both tactics are possible and have been used on other chips.
- The charge held in disconnected capacitance is usually reckoned to last on the order of milliseconds. DRAM refreshes are in that range.

It's true that depletion mode transistors are always on, but it may be worth noting that they are more strongly on when their gate voltage is higher. Therefore they are slightly more power efficient than resistive pullups, at a given speed.

Sorry, I can't follow your descriptions of transistor behaviour when written out in text: if you could supply an annotated diagram or links to visual6502 that would help.

Cheers
Ed

If five voltage or zero voltage is applied to the depletion transistor’s gate terminal, then the depletion transistor ignores the request from gate terminal while it is always turned on permanently until the 6502 microprocessor is turned off by the power supply. Why did visual 6502 show depletion transistor when it is turned on in orange node and turned off in yellow node?

If t2654’s gate terminal is pulled high, it is turned on before power source is able to detect the ground source through t2654’s n-type channel. The hole charge flows from the power source onto node 5 and the electron charge flows from the ground source onto node 5 while the current is flowing on node 5 toward the ground source from power source because depletion transistor’s n-type channel and t2654’s n-type channel are “closed” or “turned on”.

The t3065’s gate terminal is able to detect the high current on node 5, but the high current weakens to become low current in causing the t3065’s n-type channel to be “opened” or “turned off”.

If t2654’s gate terminal is pulled low, it is turned off before power source is unable to detect the ground source because t2654’s n-type channel is opened. The hole charge flows from the power source onto node 5 and no electron charge flow from the ground source onto node 5.

The t3065’s gate terminal is able to detect the high current on node 5, but the high current cannot weaken to become low current in causing the t3065’s n-type channel to be “closed” or “turned on”.

I am not certain how I can better explain these words in writing. Please explain how hole charge, electron charge, and high/low current work on any node.

I drew my diagram. The moving white thick arrow is the high current and the moving white thin arrow is the low current. You will be able to have an idea what I am saying.

I drew a better schematic than before. Each transistor has four ID numbers. Four ID numbers are drain terminal, gate terminal, source terminal, and transistor. The first drain terminal’s ID number is on the top. Second transistor’s ID number is between drain terminal and gate terminal. Third gate terminal’s ID number is between transistor’s ID number and source terminal. Fourth source terminal’s ID number is below the gate terminal.

The transistor’s ID number is colored in dark yellow.
The gate terminal’s ID number is colored in dark blue.
Both drain terminal’s ID number and source terminal’s ID number are colored in either dark red, dark green, or dark blue.

Notice that the top depletion transistor’s drain terminal does not have the plus sign in circle, but it only shows a horizontal line on the power source. I chose to omit the plus sign in circle in order to save the pixel space due to very large diagram.

All the ID numbers are needed in case if you make mistake to identify the wrong transistor in drawing the big schematic. My schematic looks very neat and clear as long as it is much better than I made my efforts to draw my own schematic and it did not look good in the past.

The color is painted in dark because it is annoying for you to read the ID number while looking at each transistor. When you sit little farther from the monitor, you will be able to see each transistor without noticing the ID number. When you want to read the ID number and compare it to visual 6502 schematic, you sit closer the monitor.

There are some node names across the schematic.

Please comment what do you think my schematic.

Bryan

Indeed, logically a depletion mode device is always on. Electrically it is always conducting, but the current is modified according to the gate voltage. Visual6502 is operating at a logical level, but of course to make even a simple inverter simulate correctly it's necessary to model the depletion mode device with some subtlety - it must pull up, unless there is an active pull down.

I think your schematics would be easier to read if you used a conventional symmetric three-terminal symbol for the FETs. See Balazs' work, and the snippets on the visual6502 wiki.

Let me try to understand what you're saying about the ALU. You mention:
- transistor t2654 whose gate is a0 and which is the pulldown of a simple inverter
- node 5 which is the output of the inverter
The idea of an inverter is that a high input causes a low output. A high input will turn the pulldown transistor on, which will dump any charge on the output node to ground, and will also sink the remaining current from the pullup, which is now weakly on. When the input is low, the pulldown is off, and the pullup's current will charge up the output node.

When describing the static situation in an NMOS circuit, it's enough to speak of what voltages are on which nodes. Currents can be ignored, as they only play a part in any switching behaviour. That's because NMOS transistor gates are capacitors, and once charged up or discharged the transistor is either on or off.

- transistor t3065 whose gate is node 5, the output of the above-mentioned inverter

As it happens, this is also the pull down of a simple inverter. But electrically that's not entirely obvious, because the output of the inverter goes through two pass gates: one (t1507) is acting as the feedback path for this storage element, and the other (t2363) is acting as a tristate control to connect the output of this storage element to the Special Bus.

It is a challenge to automate the identification of each transistor's role, as a pulldown or a pass transistor or tristate. In fact these roles are not always local properties, but they can usually be determined when taking into account the control logic.

I notice you mention hole charge and electron charge. I don't think that's useful! You only need to speak of high voltages and low voltages, which correspond to charged or discharged capacitors (aka transistor gates.) You only need to speak of currents when you are speaking of transitions from high to low or vice versa.

About your second diagram: that very shallow and compact cross-over is not a good idea. I think you should group the transistors according to the logic gates they form, and put space between them. It should be more obvious that we have two logic gates on the left side, and that they are cross-coupled. The cross-over angles should be 45 degree slopes. Make sure you use space to help the eye see where the boundaries are and which things are closely related.

Hope this helps.

Cheers
Ed

Hi Ed,

I don't understand what you are referring "conventional symmetric three-terminal symbol for the FETs". Balazs' schematic uses standard FET transistor symbol. I wanted to enhance the standard FET transistor symbol into deep detail by adding node ID in three terminals of drain, gate, source and transistor ID. My diagram is intended to allow anyone to read node ID and transistor ID inside FET transistor symbol while they read and/or compare visual 6502 website. All four identification in each transistor are painted in dark so that anyone do not have to read the identification if they do not want to do that.

Why? All 3510 transistors are tri-state. The true tri-state is not intended to be tri-state buffer symbol or contain five transistors including two inverters and one switch.

I am not sure what you are referring two logic gates on the left side. Are you talking about two inverters as latch? Look at two diagrams below.

First Latch:


Second Latch:


Which first latch or second latch diagram do you like? I prefer "second diagram from previous post I created myself" because you suggested: power is on top, ground is on bottom, input is on left, and output is on right.

Accumulator register has two inputs and two outputs. I should group two inputs as they treat to be feedback from special bus and node 146 as output from second inverter. I group two outputs as they treat to be tri-state control. I group two inverters as they treat to be latch.

Two inverters do not have SR latch. What do you call latch? Buffer latch?

If you like either first latch or second latch diagram, why did SR latch of NOR / NAND logic gate symbols show first NOR / NAND logic gate symbol on the top and second NOR / NAND logic gate symbol on the bottom by cross coupling?




Compare two diagrams of buffer latch and SR latch to my second diagram on previous post as first NMOS transistor symbol on the top and second NMOS transistor symbol on the bottom by cross coupling.

Bryan

Hi Ed,

Please look at my diagram. I made some changes according to your suggestion.

What do you think? Is this diagram big enough? Do I need to add little more details like "Input Enable", "Output Enable", and "Clock Enable"? Do you expect that more labels on the diagram is more readable?

Bryan

Hi Bryan
I strongly prefer the symbols used in your attachment latch2.png - they are simpler, and less visually distracting, than the symbols you're using now.

I do prefer the new cross-over angle and spacing!

Yes, I think it would help to label functions like clock, enable, reset and so on.

Cheers
Ed

Hi Ed,

I think three version of schematics are good idea. First version of schematic is filled with logic gate symbols and labels. Second version of schematic is filled with transistor symbols and labels, but all identification of nodes and transistors are omitted like latch2.png for less readable details. Third version of schematic is filled everything like my new diagram above. Anyone is able to choose one of these version of schematic. What do you think?

I wish anyone read my post and see my diagram. Let them express their opinion of my work. Why not?

My question is not answered. I asked what latch is called for accumulator register since it does not have SR latch. What is the name of latch? Do we call buffer latch?

Some logic gate symbols include transistor symbol. The transistor symbol is treated as a switch because buffer tri-state symbol can't be used as it has five transistors. Do you know if there are other symbols rather than showing transistor symbol on the logic gate symbols?


Is my new diagram better with the new cross-over angle and spacing?

Please advise.

Bryan

Hi Bryan
yes, I do prefer the new cross-over and spacing, but I still don't like the transistor symbols. They are too cluttered.

The A register storage elements are clocked D-type latches, I think. They have an enable and a clock. But there might be a more accurate name.

Cheers
Ed

Hi Ed,

Let me understand correctly. You like my new diagram because new cross-over and spacing are present. You don't like the transistor symbols. Are you referring that the transistor symbol contains an arrow line between drain terminal and source terminal? If the arrow line is removed from the gate terminal, then transistor symbol is more readable? No more broken line in the enhancement transistor symbol and add fat line in the depletion transistor like latch2.png. I plan to draw in the second version of schematic.

The reason is that I include the identification of nodes and transistor in the third version of schematic in order to reduce confusion and make mistakes in drawing the wrong transistor symbols between wires and transistors symbols. I have notice that there are some errors on the 6502 schematic as you mentioned a long time ago. That is why visual 6502 website becomes available.

D-type stands for data latch like RESP, NMIP, and IRQP have it. I will do more research later.

Bryan

Great, yes, if it's like latch2.png then I think it will be much more readable.

Cheers
Ed

Hi Ed,

I will like to hear your feedback about the third version of schematic. I made few changes. I added more descriptive labels. My diagram looks better. All the identifications of nodes and transistors are in very dark color.

Can my question please be answered? Are you able to read dark color labels? Can you easily ignore them while looking at each transistor symbol? Look at A Reg1.png below.

Do you like it? I hope anyone will comment as soon as possible.


The second version of schematic is on A Reg2.png below.

What do you think? Do you like color as red, green, and blue on each transistor?

I made an effort to save space by 50% Look at two diagrams below.


Which is better do you like A Reg1/2.png or A Reg3/4.png?

Bryan

Hi Ed,

I will like to show more diagrams. I think my diagram looks better. Perhaps, you like original 6502 schematic.

I like Nor Transistors.png. It shows one ground symbol.

The 6502 schematic shows two grounds on Nor Transistors2.png

I like Nor-And Transistors.png. It shows one ground symbol and left transistor is in the center position.

The 6502 schematic shows two grounds on Nor-And Transistors2.png and left transistor is in the top position.


Please comment which symbols do you like?

Bryan

Hi Bryan
the simpler transistors in images 2 and 4 are much better.

As for the dark labels, no, sorry, I can't see them. Only with the monitor turned up painfully bright and with 300% scaling can I see them. Bear in mind that I'm in my mid-50s. Well, early 50s. As we age much less light gets into the eye.

But trying to label everything everywhere is probably not a good plan - knowing what to exclude can be as important as knowing what to include. As a simple example, you have A0 appearing twice - where it is made, and where it is used. That's redundant when the wire between them is relatively short.

On your second post: you like to connect all the pulldowns to a single ground. I think this makes for more clutter and makes the shape of the pulldown tree harder to see. Separate grounds is visually simpler, and exactly the same electrically.

On the transistor colours: maybe it helps to use a different colour for pass gates, but blue is a bad choice I think, if you are going to use colour at all, because it's the same as the wires. Maybe yellow would be better.

Cheers
Ed

I find the black background makes it very difficult to read those diagrams.

-Tor