Nothing really new or particularly clever on my part (it's pretty much all been done before), but it's my first ever SBC design so I'm pretty geeked.

This is basically a ROM-less SBC with an R65C02 CPU running at 1-MHz, a 64K RAM chip, and a PIC microcontroller "helper". The PIC provides the 6502 reset and 1-MHz clock signals and it loads RAM during power-up or after a reset with a pseudo ROM image from flash memory. The PIC also eliminates the need for a GAL or other discrete logic ICs for address decoding by implementing a soft decoder with single page resolution for up to six chip select pins. The soft decoder also maps the PIC UART to a single page in 6502 address space and the UART presents to the 6502 as a simple 6850 ACIA.

To test the SBC I modified the soft decoder 256 byte "decoder map" to fill the 64K address space with RAM, except for the $DF page where I mapped the UART (pseudo ACIA). I also uploaded Grant Searle's ROM image of OSI BASIC + Monitor into PIC flash memory and this image is copied into RAM at $E000-$FFFF during start-up. Everything works great!

I'm in the process of moving the design from a solderless breadboard to a 2.0" x 2.75" prototype board and there's lots of work left to implement a "supervisor" mode on the PIC to allow uploading decoder map and ROM image files via the serial port into flash memory.

This SBC design is the result of help and inspiration from many sources across the internet and here at 6502.org.

Cheerful regards, Mike

Looks terrific, Michael!

Can I ask you to elaborate on the PIC, please. For the address decode function, is the PIC actually inputting the 6502 addresses and -- in software -- testing for matches and updating chip selects (or UART access) in response? A tight loop accessing a lookup table, perhaps? The clock rate would need to be pretty high... several times faster than the '02, at least.

I like the idea of a pseudo ROM: RAM loaded with an image from flash memory!

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Hi Jeff:

My address decoder method uses an array of 256 bytes with the high byte of the address buss (b15..b8) as the array input (index), representing pages $00..$FF, and each element in the array contains the bit pattern for the six chip select outputs (port C, b5..b0) for that page. So, each chip select output has 256 bits spanning the array (or "decoder map", if you like), one bit for each memory page, that defines its state for that page. The PIC is running much faster than the 1-MHz clock it's producing, and since it's producing the clock, it knows exactly when it can sample valid address data each cycle. The PIC has just enough time during each 6502 cycle to read the address and use it as an index to copy the correct element from the array or "decoder map" onto the chip select outputs.

Does that explanation help?

Regards, Mike

Congratulations on getting it working. This is similar in concept to Jac Goudsmit's Propeddle http://propeddle.com. I recently bought a Propeddle from Jac and I'm modifying his Propeller firmware to act as a 6551 also.

How are you using the Pic's uart from the 6502? Does the Pic's decoder code know that certain addresses go to the Uart instead of ram?

Jac's explanations were great help when I started this project, as were examples from Nicholas FitzRoy-Dale's Hardware SID Player article. Other Wizards here on 6502.org (Garth, Daryl, Grant, Andrew, Klaus, and others too numerous to mention) have contributed in many ways, not to mention putting up with my silly questions and emails.

Very cool. Good luck. I'd love to have a Propeller chip to play with (sigh).

The PIC UART is mapped into 6502 address space much like any other device, except that PIC I/O doesn't require an external chip select pin. The decoder maps eight bits to each page of memory but only six of those (b5..b0) are written onto the PIC chip select pins during each 6502 cycle. I use one of the left-over bits, CS7 (b7), to map PIC I/O into the address space. Here's an excerpt from the decoder map table for my current memory map to give you an idea of what I'm doing;

After the PIC updates the chip select pins during each 6502 cycle, it checks bit 7 in the working register, WREG, which still contains decoder data, to see if the 6502 is requesting PIC I/O. If it is a PIC I/O request, the PIC simply pushes/pulls UART status or data to/from the 6502 data buss to match the request.

The current PIC firmware presents the UART as a 6850 type device with address $xx00 for the ACIA Control (wr) and Status (rd) registers and address $xx01 for ACIA Data (rd/wr). The current memory map places PIC I/O in the $DF page so the ACIA registers show up at $DF00 and $DF01 (and are repeated 127 more times within the page).

Hope this helps... Good luck on your project...

Cheerful regards, Mike

Good job!

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

This is really impressive!

I know very little about PICs but I really like the fact that the one in your design apparently has enough pins to connect the entire 6502 address bus and data bus and then has enough pins left over to do address decoding. You've already proven that emulating the OSI is easy for programs that don't access the OSI video memory directly. The Apple 1 should also be easy to emulate: the original hardware doesn't even have direct video memory access.

The audio/video output (TV or VGA) is my favorite feature of the Propeller but it takes up so many pins on my Propeddle project (http://www.propeddle.com) that I had to add 2 chips to multiplex the address bus into the Propeller, and some tricky code to get the timing right. Not to mention a third chip for the signals (IRQ/NMI/RDY/SO) but you don't really need those in many cases -- certainly not for the OSI or Apple 1. The way you did it, I suppose you can always create an expansion board with a Propeller, and do video (and keyboard and mouse and other hardware, SD card maybe?) with just two more chips (the Propeller and an EEPROM), and you'll still use fewer chips than the Propeddle project!

I got a question though: Where did you get the UM61512A? I decided to use half of a 128KB chip (AS6C1008-55PCN) because the Big Three (Digikey, Mouser and Jameco) all didn't have a 64K SRAM chip, surprisingly.

Thanks for sharing!

===Jac

Thank you...

Hi Jac. What a nice surprise. Nice to meet you.
Thank you. That means a lot since you've "been there, done that" working through the timing requirements for this type of system.
Yes, this particular PIC has worked out well and I'm very pleased that the decoder sub-system actually works.
Well, I'm not really trying to emulate an OSI. I'm just taking advantage of Grant's work extracting that particular flavor of BASIC from the pagetable site and the work he's done to put it into a single file that can be modified and assembled easily using CA65.
Yeah, it's surprisingly simple if you get rid of the video/keyboard. Relatively easy to duplicate even with this 3-chip design. I plan to upload an Apple-1 decoder map file and the Apple-1 Woz' Monitor + BASIC files into flash memory via the PIC "supervisor" mode for testing in the next day or two. Then I'd very much like to add video/keyboard support, a "slot", and turn it into a modestly priced product.
Video, keyboard, SD card, and more are definitely on the horizon. I'd love to try a Propeller. Do they sample? Anyway, a PIC 32MX in a DIP-28 package with 32K RAM and a couple DMA channels looks like a good candidate for Video/Keyboard/SD Card at this time.
That was a donation from a Ham radio friend. I think he got them on ebay. He actually offered me a choice of that 64K chip or a 128K Alliance chip like the one you're using. I snatched up the 64K chip because it was 15 nanoseconds and because it would fit within the open frame of a 40-pin machined pin socket.

Hey, thanks for the shout and encouragement. Twas' a pleasure meeting up with you.

Cheerful regards, Mike

I just built Vince Briel's Replica 1 Tenth Anniversary Edition and found out that it also has a great interactive 6502 assembler on-board called Krusader. It's not mine but I definitely recommend it as a way to bring up a 6502 system in an easy way. It was written for the Replica 1 but should be easy to port to other "platforms".

If you're going to sell this as a kit, I would definitely be interested in buying it! Keep us posted if you going ahead with this.



Parallax doesn't give out samples, but the Propeller is not that expensive (about 7 dollars US - yes, more expensive than a PIC but they say you get 8 processors for the price of 2 ). And maybe I can help, I'll send you a PM.



The Alliance chip is 55 nanoseconds which should be fast enough to run a 6502 at 14MHz or so. Fitting "inside" the socket of another chip is a nice advantage indeed. It makes for a nice small PCB, though I bet you have to use a 4 layer board for the one in the picture. Or not?

Oh and I forgot to mention, I like your breadboard version too! My first breadboard version (which was "Frankensteined" with a Briel Computers Pocketerm) didn't look nearly as nice



Same here! Keep up the good work!

===Jac

Hey Jac,

I would definitely specify the Alliance chip if it was going into a product where you need reliable product and source.

I'm not sure how many layers I would need for that little 2" x 2.75" board. I haven't tried routing it. Please keep in mind that I can mix up the address lines and the data lines on the RAM for best routing. That is, A1 on the RAM does not have to go to A1 on the CPU.

That breadboard doesn't look bad at all...

Cheerful regards, Mike

Project Status Update

I'm still wiring up the 2.0" x 2.75" prototype board and there's lots of work to do on the PIC microcontroller firmware for the PIC "supervisor" mode which basically provides a way to upload a 256 byte "decoder map" file and ROM image files via serial port to flash memory in the PIC. I suspect that Daryl's method of auto-booting his AVR 6502 Emulator into 6502 mode with a time-out to invoke the supervisor may be the cleanest and most intuitive method.

Once the project is a little more complete and polished I'll post it in the SBC forum along with documentation and firmware. I'm also thinking about making a couple different PCBs available, if anyone is interested.

A three chip Apple-1?

Well, almost. Any respectable Apple-1 replica would need another chip to interface a keyboard and produce composite video, as well as a 44-pin "slot" for expansion, but I felt compelled to try out a Serial Apple-1.

I modified PIC code to present the UART as the 6821 PIA used in the Apple-1. Then I modified the decoder map to assign chip select pins for the Apple-1 $Axxx, $Bxxx, and $Cxxx expansion I/O address space. The UART (pseudo 6821) is mapped to the $D0xx page and RAM fills the remaining space at $0000-$9FFF and $D100-$FFFF. An image of the Apple-1 Woz Monitor was installed in flash and is loaded into RAM at $FF00-$FFFF during start-up.

While it may not look like much (the Woz' monitor only has about three functions), anyone who knows anything about Apple-1 history will understand why I got goosebumps (and a big smile) when I started using the Woz Monitor.

Wow, what a nice start of a clean Apple 1 clone! Woz needed a board full, Vince made a much smaller system of it, but this 3 IC design is still a real 6502 with the same software . It makes me have a big smile also!

Awesome stuff again. Yes, big smile here too

With a setup like you have, producing many different emulators with the same hardware is obviously pretty easy.

===Jac

This is awesome! I saw it on hackaday and was immediately excited because I enjoy any SBC. Could you make a video of you using it?