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PostPosted: Mon Jan 13, 2014 10:16 pm 
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Hello everyone,

I’d like you to inform you about a nice system I encountered.
My son is following a subject "Computer Systems" and to my surprise it involves a practicum with a so called "PP2 practicum board", an assembler written in java, an emulator also written in java and the complete documentation.
Attachment:
PP2ManualB v2 identical_page2_image1.png
PP2ManualB v2 identical_page2_image1.png [ 465.37 KiB | Viewed 1356 times ]

The development board consists of a Spartan 3E on a (which looks like) GODIL_XC3S500E board or similar.
http://shop.trenz-electronic.de/catalog ... cts_id=630
The FPGA is pre programmed as an 18-bit CPU following the Von Neumann architecture. http://en.wikipedia.org/wiki/Von_Neumann_architecture It has 20kB of 18-bit RAM. The CPU called PP2 runs at approximately 35 mhz. It has 8 general purpose registers R0-R7. The assembler and the CPU work with relocatable code and relocatable data! Data can be accessed by indexing with a so called Global Base register (equal to R6). It has a resizable Stack Pointer (equal to R7).

Further there are 8 tactile buttons, 8 LED’s, 6 7-segment displays, a potentiometer, and 3 on/off switches with LED’s, a timer and a serial interface up to 115200 baud. Those I/O devices are allocated to memory locations -1 to -16 (two complement)


Well, what does it have to do with the 6502? Easy enough:
Code:
LOAD
ADD
SUB
CMP
MULS
MULL
DIV
MOD
DVMD
AND
OR
XOR
STOR

JMP
JSR

BRA
BRS
BEQ
BNE
BCS
BCC
BLS
BHI
BVC
BVS
BPL
BMI
BLT
BGE
BLE
BGT

RTS
PULL
PUSH

It’s very easy to adapt and write in that assembly language. One feels instantly at home. :)
As far as I can determine, branch instructions can reach the whole address space of 18 bit in two complement. So from -131072 upto 131071. That’s fantastic. It has no shift instructions, but those can be achieved by MUL and DIV. Multiplications can be 18 bit with overflow (MULS) or 36 bit with overflow (MULL). Wow.

Does anyone of you know of this system?

Making such a similar board based on the W65C02 or W65C816 would be great for newbie’s (including myself). Providing a complete manual and a number of exercises with solutions in PDF format.

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PostPosted: Mon Jan 13, 2014 10:30 pm 
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I'd be interested to know how the DIV is implemented!


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PostPosted: Mon Jan 13, 2014 10:43 pm 
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Quote:
DIV reg := reg div operand
The quotient of reg and operand is assigned to reg , the remainder of the division is discarded. It is a (required) precondition of this operation that the value of the operand be positive, otherwise the result of the operation is undefined. The condition codes are set as follows: Z indicates whether the (discarded) remainder equals 0 , N indicates whether the quotient is negative, and V signals that the value of the operand was not positive.


There is also a MOD command for the reminder. And also a DVMD command which places the quotient in reg and the reminder in reg+1.

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PostPosted: Tue Jan 14, 2014 8:27 am 
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Do you know any cycle counts for the MUL, DIV and MOD operations?
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Ed


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PostPosted: Tue Jan 14, 2014 10:40 am 
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The documentation doesn't specify any cycle counts, however, they give an indication that turns out to be fairly accurate.
Quote:
Every (read or write) access to memory requires one clock cycle. ... almost all binary instructions with indexed addressing with a short displacement or a register are executed in 2 clock cycles. Exception: independently of the addressing mode, the division instructions DIV , MOD , and DVMD require two clock cycles more than the number of memory accesses, because division is more complicated.

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PostPosted: Tue Jan 14, 2014 2:45 pm 
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I've never heard of the "PP2" architecture. It seems like a very logical instruction set, though, almost a mini-RISC.


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PostPosted: Tue Jan 14, 2014 6:23 pm 
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I guess it’s solely for educational purposes. And PP2 probably stands for Practicum Processor 2.

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PostPosted: Tue Jan 14, 2014 7:13 pm 
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Very interesting - a 2-cycle divide, or thereabouts. If there's any public information about the system or the CPU architecture, I'd be interested to see it!

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Ed


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PostPosted: Wed Jan 15, 2014 2:26 pm 
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I can’t find anything on the ‘net about it. I only have a copy of the documentation for students, exercises, emulator and assembler.

It’s property of:
Rob R. Hoogerwoord
department of mathematics and computing science
Eindhoven University of Technology

I have no idea what the chances are for getting and using the sources for our own uses. But I doubt it regarding students might copy and paste possible solutions from the net.

I had hoped someone knew all about it here on the forum.

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PostPosted: Sat Jan 18, 2014 3:44 pm 
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Some promising news about the PP2 development board.

My son and I have sent an email to the responsible lecturer of the subject in question and asked if he would share the HDL sources of the PP2 and the schematic for the development board. Furthermore I mentioned 6502.org and it’s purpose, and asked if we may share the sources with the forum.

He answered: (translated)

The PP2 processor is entirely made by Rob Hoogerwoord. I send this mail to him so he can decide whether he wants to share the design. I see no reason why it could not.

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PostPosted: Sun Jan 19, 2014 4:21 pm 
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Very hopeful- thanks for following up!


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