Last time, I asked more information about Donald Hanson's 6502 block diagram such as what was the last letter 'P' and 'G' and 'L' of NMI, RST, and IRQ. Ed answered as saying he only guessed to name the node and his answer appears to be correct, but I do not have chance to analyze data of transistors yet.

I focus on timing generation logic and random control logic.

I need your feedback. Can you guess what are six labels in random control logic? Six labels are POS, NOCR, SD1, SD2, CS, and I/V. NOCR looks like no carry. I/V looks like interrupt and overflow flag. After I get your feedback, I will be able to continue my work to analyze more data.

I create two version of schematics. One is transistor level and another one is logic gate symbol.

I had read several posts on this Visual 6502 discussion. Someone wrote 6502 Simulator in Java and C++ source code. My question is why there are too many branches such as IF / ELSE. They can lead to branch mispredict to slow down the simulator project. I know the only way is to eliminate all branches and use only one main loop such as while or do while. The main loop executes a function called MPU6502_Run() before data in all states of transistor will be modified during one cycle. After one cycle is completed, it returns back to the main loop and repeats the same function MPU6502_Run() for thousands of cycles. I am certain simulator will run much faster with small memory about one megabyte and improve the cache.

Bryan Parkoff

I can tell you that POS is very probably pipeUNK13 in the visual6502, and indicates a positive number. What happened is that Donald Hanson wanted to write an accurate simulatable description of the 6502, and he got hold of original blueprints. He then got the block diagram drawn up with the help of a draughtsman. Some of the names on the block diagram are likely to be his own invention and others are likely to be taken from the original blueprints. Those blueprints (photo at http://www.flickr.com/photos/textfiles/9013110403/) are not publicly available, although you can find other schematics - for example at http://blog.kevtris.org/blogfiles/6502_2/ and of course Balazs' schematic, which certainly contains his own invented names for signals and state.

As we now have the visual6502, we know that there are a lot more bits of state than are labelled in the block diagram.

Please provide links to the Java and C++ simulators you mention.

Note that all the approaches to transistor-level simulation are iterative in nature. The 6502 is not made of logic gates, it is made of transistors. In particular there are two sets of 8 pass transistors which connect the various internal busses and which operate bidirectionally. No-one, to my knowledge, has solved the problem of simulating these pass gates without iteration. (Nor, to my knowledge, has anyone solved the problem of auotmatically determining which direction all the other transistors operate in.)

Cheers
Ed

Hi Ed,

Thanks for your feedback. I have read blueprint website before. Thanks to Visual6502 tool to help me in tracing transistor by transistor level before I am able to draw logic gate symbols. This is VERY complicated and DIFFICULT to understand from the beginning, but now I understand ALMOST all! I did not have chance to write notes to explain how transistor by transistor level's behavior is. I will finish my notes after I finish to draw the schematic.

Forget about original blueprint. My schematic will be available at later time when I am ready to announce. Do you mean PIPEUNK?? to be pipeline? Why there are so many unknown names? Nobody is willing to invest their time to label more new node names. I take over and fill the gaps.

You did it! You read and discussed posts with anyone a long time ago. I can tell you 8 pass iterators and IF / ELSE can be eliminated. Write logical AND, OR, and NOT such as extra logic gates into single transistor. Extra logic gates in single transistor is hidden before one or more transistors can form into true logic gates like true Visual6502's behavior.

I have not written my code yet, but I plan to do that soon.

Take care,
Bryan Parkoff