Either a CPU with 16-bit registers and ALU, but a 32-bit data bus, or a CPU with 8-bit registers and ALU, but with a 16-bit data bus.

It might sounds wasteful, but it would have the benefit of having either an immediate value or absolute address within a single instruction word. It would need to have a 68000 style data bus, where the top and bottom halves have their own R/RW signal.

Most of the Pentium-class and up x86 32-bit processors had a 64-bit wide memory bus. I wouldn't be surprised if Power, Sparc, etc, do or have done the same. Basically, once you add a cache you can effectively decouple the bus from your registers.

I wish somebody would start producing these: http://www.venraytechnology.com/Implementations.htm It's hard to tell the details on the newer stuff, but the original design is for a 4096-bit wide bus right in the DRAM chips themselves, for single-cycle access to an entire cache line.

Intel's Haswell systems with the 128MB of L4 cache gets into somewhat similar territory, though that's not actually the external data bus to main memory.

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WFDis Interactive 6502 Disassembler
AcheronVM: A Reconfigurable 16-bit Virtual CPU for the 6502 Microprocessor

PIC microcontrollers (up to PIC18-- I have not looked beyond that) have an instruction bus that's 12, 14, or 16 bits although they only handle 8-bit data and their data bus, working register, file select registers (FSRs), I/O registers, etc. are only 8-bit. So they can have MOVLW H'61' (MOVe Literal to Working register) for example all in one memory access; but it still takes four clocks, whereas 6502 only takes two clocks for the equivalent LDA #$61.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?