I've been looking up CPU stuff, and the talk about the new 65org16 CPU caught my attention. Is there any programming manual for the 65org16 yet? Is it exactly the same as the 6502, only everything is doubled in bit size?

Apparently there are also different variations of the 65org16 CPU with additional features and instructions. Do any have an "ADD" or "add without carry" instruction?, because the lack of an "add without carry" instruction is something that has always annoyed me with the 65816, and it looks like it would be an obvious thing to fix.

I'm sure ElEctric_Eye will be along to answer the questions better, but until then, I think the 65Org16 is basically a double-wide NMOS 6502 as far as instruction set goes-- although he was experimenting with some other ideas with registers, etc. too.

As far as the ADD instruction goes though, doing a single-byte, two-clock CLC first when necessary is pretty tiny overhead, and it seems to be that the designers decided that adding the ADD instruction (and other nice-to-haves) would not improve performance enough to make up for the fact that the added instruction decoding would reduce the maxium clock speed. You can of course make ADD macros that hold the CLC inside but don't make you look at it every time.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Welcome Aaendi, BigEd has a nice thread summary of the 65Org16 that should present enough details for you.
BTW, what programming languages do you work with presently?

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

The only thing that I have programmed is the Super Nintendo.

Ah, ok I was just curious myself. I had posted the spec's of the .b version somewhere. I'll post it here.
Most of the ideas were inspired by Arlet Ottens, creator of the original 8-bit core, although I implemented them in the final Verilog...
The next version is .d, which I currently work on and test in a 70 MHz FPGA real world (at present video only) system I custom built. I need to update quite abit of information. I'll do this as demand presents itself, otherwise I won't waste my time.

The .b core spec sheet is not presented in the most elegant or well explained fashion, but I'll try to entertain any questions as best I can.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

(You can read EEye's doc in your browser at https://docs.google.com/viewer?url=http ... p?id%3D718)

I find it strange that the 65org16.b allows registers as both the source and destination, but not as the second operand for ALU instructions, though I could see the reason for that.

That's because it's easy to use B instead of A. It only requires that the core selects a different register. For operations between A and B, you need to change the design quite a bit, because it's a completely new concept.