There are these 2 non overlapping clock cycles in the 6502. I wonder if there is a high level view of why this is so and what happens at each cycle. I'm analysing the processor right now, but I sometimes feel like I'm lost in the trees when I want to see the forest. So what would be the forest in regards to the clock cycles?

The basic flip-flop structure in NMOS is a pair of D-type (transparent) latches: such a pair is a reliable edge-triggered flop provided the two clocks don't overlap. A latch (or half-latch, depending on terminology) is as simple as an inverter with a pass gate on the input: just 3 transistors.

One design style would interleave logic clouds with edge-triggered registers, but another is to interleave logic between both halves of the flop. You'll probably find both examples on the 6502: another way to look at this is that some signals have a deadline which is the falling edge of phi1, and others have a deadline which is the falling edge of phi2.

Have a look at http://en.wikipedia.org/wiki/Flip-flop_ ... _flip-flop - it might help.

Cheers
Ed

You might also find these helpful:
http://visual6502.org/wiki/index.php?ti ... 2_datapath
http://visual6502.org/wiki/index.php?ti ... te_Machine
http://visual6502.org/wiki/index.php?ti ... ck_Diagram

Cheers
Ed