If you start the simulation you will see that the predecode register (pd0-pd7) starts in a powered state right at the beginning before any step is executed:

http://visual6502.org/JSSim/expert.html?nosim=t&find=alu4&panx=528.7&pany=211.0&zoom=10.7

1. If I understand the gates correctly the only way for those nodes to be powered is through the transistor below them controlled by the cclk signal. cclk has to be up at least once before they can be powered. So how comes they are powered right at the beginning of the simulation? I notice the same pattern in some other nodes that start powered.

2. Also they should discharge when cclk is down, correct? But I suppose the latter is again a timing issue, they won't discharge during one clock cycle, am I correct?

EDIT: OOPS, I just realized when I follow the link I posted they in fact aren't powered. But when I hit reload on my simulation they start powered. I guess it's a problem of the simulation retaining state when you hit reload on the browser(Firefox here).

Note also that the simulation pre-runs for a few half-cycles, just like the real 6502 likes to have a few clocks with reset active, to initialise state.

(I'm using chrome, and I don't see anything different on a reload compared to a fresh window.)

I single-stepped forward and then back, to land on half-cycle 0, and indeed 'pd' is $ff. It looks like pd is the inverse of the databus, so probably for the simulation, prior to time zero the databus is zero.

(You can use &logmore=-pd or put -pd into the Trace these too box to get an inverted readout - which would be a true readout.)