I just looked over the instruction set for 8051 and lo and behold, it too has a DJNZ instruction. The 8051 arrived well after the 6502, I wonder why it became so popular while the 6502 is now relegated to special purpose application. I would have thought that a processor acceptable for pacemakers would also be acceptable elsewhere.

Well, it is a question of application and target audience.

My personal view, based on having programmed a lot of low level code for a lot of different architectures, is that the 6502 is a supremely pleasant processor to program in assembly code. Code density is impressive and I remember on project I did with a colleague, implementing a complete Huffman compressor in about 700 bytes code (that is bytes, not KB). A view on Opencores show a lot or re-implementations but actual use in end user products is less visible. At the same time ARM, Atmel, PIC and others are doing a roaring business.

I think there is a place for 6502 though a few improvements would be in place such as various extension to the instruction set suggested. An updated SWEET16 implementation would extend into 16 bit space where ARM enters using the Thumb profiles.

Another possibility is more fundamental hardware changes such as making $0000 - $03FF 2-port memory which should shave off a lot of cycles for zero page access and stack use. This should still remain transparent to the programmer. Shadow registers for fast interrupts is another possibility, as is a fast bank for interrupt code (say, at $C000 - $FFFF). Perhaps a nice development board is all it takes to bring the 6502 back into the limelight.

Hmm, what's your 2-port memory idea?

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Oh, I see/remember: by dual-port memory is meant that the core has several paths to memory so fewer cycles would be needed to execute complex instructions. Transparent to the programmer, indeed, but a major difference in the core. All you need to do is become or recruit an HDL designer and your wish will be granted!

(The reason WDC only offer mask ROMs will be one of manufacturing process: mask ROM is cheap and easy to make, same process as normal, whereas reprogrammable technologies are another thing altogether.)

Cheers
Ed

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

It's not so much the connectivity of the memory as the change to the bus structure of the core and the implied change to the sequencing which means rework (or a new core) - a few words of English might mean a whole heap of HDL. A picture is always a help. To my way of thinking, implementation is the bottleneck, not ideas. Those few ideas which bring a big gain at low cost are very worthwhile, but even then, only if there's someone to make them real.

(For a thousand units or so, don't FPGAs fit in? I suppose skillset might be as much a problem as economics. For the major manufacturer, an ARM-based SoC running at 168MHz programmed in C might be cheaper to make and support, and sell in higher volume and give just as good a power/cost/performance solution as the 8-bit SoC you wish you could buy.)

Awesome. I had no idea the 6502 was that popular. I was told ARM volume was counted in billions, seeing 6502 hot on the heels like that is quite the surprise to me. Can you say more about where these go?


I never expected a single instruction to propel the 6502 to the forefront of the big volume league. As you mention above and as we remember from Z80, performance or convenience is low down on the list of what clinches the deal. Still, to get into the current mindshare a little activity is a lot better than a slumber where little news happened since the 1990's. A little improvement here, a little speed up there, a few new family members over there and trade press coverage changes. The 6502 might be a wonderful gem of a processor but that is little help if it is only known by people who rememebr it back from the 1970's.


If we provide a complete 1 KB (range $0000 - $03FFF) we get another 2 pages that can be used for a lot of other tricks and would also be nice for the architectural variations that provide a direct page register.


I quite agree performance is not all. ARM got a long way by focusing on the MIPS/Watt ratio.Then they extended the architecture all over the place: downward with 16-bit Thumb, upwards to 64-bit architecture, sideways with several rounds of DSP add-ons plus various bits and pieces like Jazelle.

For the 6502 I believe high useful MIPS/MHz, very high code density (further improved by SWEET16) and very low transistor count (and thus consumed chip area) are the main drivers. High reliability and a pleasant programming experience is most likely quite a way down on the list of decision factors. Still, the 6502 has what counts and has it in spades.

Exactly. This makes the previously multi push instructions more convenient. Registers can be pushed onto the stack while the CPU works on the next instructions. This would either need careful interlocking of a very careful programmer.

A second use is a stack dup: read top of stack through port 0 and copy this value to the stack using port 1 while next instruction is decoded.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Speaking of which, I thought I'd toss out yet another idea: change the pre-indexed, zero-page indirect address mode to pre-indexed, absolute indirect. I don't use (zp,X) very often, and when I do the X-register usually equals zero anyway. If the instruction was instead absolute (like the 65C02's JMP (ab,X) instruction) then I could do things like this:



Because the instruction would be absolute I could also do:



to get at things below the initial stack pointer, ie., the stack pointer could be used as real base pointer. At the very least I can see using this address mode more often than the original 6502 version.

Simpler might be just to hard-wire the high byte of "ins (addrlo,X)" to be $01 instead of $00. That wouldn't let you get at anything below the initial stack pointer, but still might make it a bit easier to use the hardware stack to pass subroutine arguments.

And the 65xx family continues to be a major attraction for homebrew enthusiasts like us. Working with the 65xx family is hard enough to keep you challenged and easy enough to keep you interested. That's a lot more than can be said for most other microprocessors.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

You can effectively do all that with the 65C816. Although it still has (ZP,X) addressing, the use of a 16 bit X-register extends the reach well beyond zero page. However...you can relocate ZP anywhere in the first 64 KB you want it to be.

Also, look at the stack relative instructions the '816 offers. Something like LDA 1,S (get last item pushed) and LDA (1,S),Y (treat last item pushed as an indirect address) gives you a lot of flexibility and you use no RAM other than the stack itself.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

Oh, I know about those, since HXA supports them. Never used them myself because I've never programmed a 65816. I'd prefer to have them - mainly because of how easy it would be to access a pointer passed on the stack - but I was thinking of something that might be fairly simple to do to an existing core.

I once heard that SWEET16 was inspired by RCA 1602. Both have a few things in common, including
- a register bank of 16 registers (1802 has a few others too)
- each register in the register bank is 16 bit wide
- instructions, on the other hand, are only 8 bit wide

I noticed that the RCA 1802 was followed by the RCA 1805 having an extended instruction set and in this instruction set a DJNZ-like instruction was added. All in all it seems this instruction is more popular than I thought.

The RCA design is quite interesting with a few unusual features such as IO straight into the core of the ISA. Unfortunately it had a separate 8 bit accumulator. I wonder if it had been more efficient with an accumulator pointer (similar to the index register pointer) to freely position the accumulator within the register bank.