I was gone all day and it has been hard to catch up on everything tonight. It has been pretty crazy, and I have not been able to read the Altera ap. note referenced above yet, but I'll try to write some things here, then come back later with more, depending on the questions & comments. Dr. Howard Johnson is an industry guru on high-speed digital design, and I've kept many, many of his articles in the trade magazines over the years, and you can find most of them on the web. Our stuff is very slow compared to what he is usually addressing, but our parts are bigger too, and pricewise, we may not be able to afford going to the lengths on our boards that he deals with. I see BDD posted while I was interrupted in my writing, but I'll keep going here anyway.
I know a good number of you have more experience at more up-to-date design principles than I do, so I beg to pick your brains.
In the past, most of my designs have been for slower systems (<= 4MHz). Now I'd like to up that to 20MHz. So, my questions are as follows:
Consider the rise time of fast parts too. It's a major issue.
1) Do ground and VCC planes cause more problems from added capacitance than they solve WRT noise suppression at these frequencies?
No. You must have a gound plane. Vcc plane is a further improvement. Without the Vcc plane, you can bypass Vcc pins to ground super close to the pin, but that's definitely second-best, not the preferable way. BTW, having a ground plane eliminates the ground bounce up to the ground connection of the IC, but there's still inductance between where the pin is soldered and up the pin and through the bondwire to the die, and that will cause a little groundbounce with fast switching times; but you can't do anything about that part.
2) Do ground or VCC connected inter-trace copper pours help keep the noise down?
No. Copper pours are helpful for high
-impedance circuits where one trace can couple into another by capacitive means. The AC-signal part of high-speed digital is low
-impedance, and the major thing is the inductive coupling and inductance, and for longish traces, transmission-line effects. To keep a line from coupling into other traces, the trace needs to run along a ground plane. The return current in the ground plane does not
take the shortest route, but instead goes directly under the trace, taking the shape of the trace, because the mutual inductance makes that the path of least impedance. If the plane is interrupted, it's no good for that. It has to be continuous; so pours don't qualify.
3) Hence, which are better, voltage planes, or inter-trace pours, or both?
Forget about the pours. You can do them if you want, but don't expect them to help.
4) Are there any other critical things I may need to know to avoid grief at these clock frequencies?
Make the board (or at least the high-speed part of it) small, and put parts close together so as to minimize the trace lengths.
Use chip capacitors for power-supply bypass as their inductance is a lot less than leaded capacitors'.
I don't limit my traces to 0, 45, and 90°. I do it however gets me the best density, shortest traces, best manufacturability, etc.. I've never had any trouble with .015" vias on .062"-thick board, or even .008" vias on .032"-thick board. The narrow (eg, .006") that BDD was talking about are not delicate like some might think. I've laid out dozens of extremely dense boards for our products, up to 500 parts and 12 layers normally .006" trace & space and .015" vias, with pads .020" bigger than the holes (so for example a .015" via has a .035" pad).
related posts (with "&start=" in the URL to land you right on the post so you don't have to scroll down to fing it):viewtopic.php?t=138&start=1viewtopic.php?t=152&start=11viewtopic.php?t=1745&start=2
Removing the "&start=__" at the end will show the earlier posts where the questions were asked.
If you want to email me your layout (or post it for everyone to see on the forum) to look at before you get it made, or even before you're done, I'll look. jpegs would probably be easiest for me, but I can take gerbers too and look at them with the gerber viewer so I can zoom way in, view a different combination of layers, etc.. I've done a lot of layout, including switching power supplies which are particularly nasty because of the astronomical di/dt's, and gotten outstanding performance.