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Going beyond two-layer is where the cost starts going up more because they have to make multiple thinner boards and then laminate them together.
The cost differential is coming down and square inch for square inch, a four-layer board is about 60 percent the size of an equivalent two-layer design. The advantages go well beyond physical size. Four-layer designs, in which the inner layers handle power and ground, are potentially a lot less noisy, generally allow increased component density (you're not having to use up space for power and ground runs) and greatly reduce voltage fluctuations and ground bounce, the latter which sabotages a lot of designs.
Yes, and although I've said that many times before, I should have repeated it. (Don't forget to count the set-up charge though, as it is probably independent of board size.)
The tendency is to think that the ground plane is to reduce the DC resistance of the return, and to think that the ground plane allows the return current to take the shortest possible path. Instead, what happens is that the return current through the plane takes the shape of the trace above it whose current it is returning. The equal currents running in both directions right near each other cancel out that trace's inductive reactance and its antenna effect. A "pour" does not qualify since the current can't get through interruptions in the copper. It has to go around, and then you have a big loop again, like a coil. In fact, that's exactly how some cell-phone antennas are made-- running the trace over a cut in the ground plane.
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I did my POC unit on a four-layer board and it proved to be stable at 12.5 MHz (maximum speed the I/O hardware would tolerate). In fact, in a fairly recent test, I removed all the decoupling capacitors and it still was stable at 12.5 MHz. That would be attributable to the fact that the inner power and ground layers act as a giant bypass capacitor and were able to sink most of the switching noise. However, don't take this to mean you should forego decoupling caps. Any good design will have one for each active device on the board.
I believe I read somewhere, probably in Dr. Howard Johnson's articles on high-speed digital design but I can't find it now, that two parallel plane layers have no inductance at all in getting the power and ground connections to all the ICs. IOW, it's the best of all worlds-- getting rid of the both the inductance and the requirement for local bypass capacitors.
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