I've come across a huge number of these (more than I could use in my life). If anyone is interested in having some of them let me know. How about $2 per unit + mail + $3 for me to drive to the post office and home? Not trying to make any money, just sharing.

If this is not appropriate, please delete it!

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Bill

Not inappropriate at all. You are helping out the 6502 community even if you expect payment. These are not officially in production anymore, although supposedly WDC will be selling them in a 14MHz+ version if they ever decide they're satisfied that they got the last bug out. There is a tiny chance I would want them for a future project (I have plenty for myself, but this would be to help others get going) but I cannot devote any time to it at all yet. Approximately how many do you think you have? Are they all in the 28-pin DIP?

I have over 100 6512's (1MHz NMOS) that I got for something I never went through with. I wouldn't mind selling them but I doubt anyone will ever want them.

HI Garth,

I could let 60 of them go, that would leave me plenty for my uses. Yes, they are all 28-pin DIP.

I feel a bit guilty about asking a nominal charge for them, but being a member of the "fixed income" crowd, I need to make sure that helping out does not end up costing me too much.

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Bill

Perhaps you could use them as chess pieces.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

I have a different collection of worthless ICs for practicing J-leading or other special assembly tricks or experiments I might want to do.

What are they good for? According the data sheet they only differ from the 6502 with the clock inputs and the Bus Enable input.

Are you interested in swapping?

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Was that question for BillO or for me? I got the 6512's because they were very inexpensive at the time (years ago, long before 6502.org existed) and I wanted to do something like Daryl is doing now in providing low-cost SBCs for hobbyists, schools, and anyone else interested. Plans changed. I'd be open to trade, if indeed anyone has any interest in them.

For you indeed.

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You can always build a multi-processing cluster out of them for kicks, and get yourself a mention on Slashdot.

Not sure exactly why you'd want that, but it's something you could do... ;D

kc5tja,

I am very interested in a "multi" 6502 processor system, but not sure how to go about even the very basics.

How could one make 2 6502's work in tandem to increase throughput? in a very simple system with:

2 Data inputs: keyboard & ROM.
1 Data output:display
2 Data I/O's: RAM & external storage

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Since the 6502s use nearly 100% of available bus bandwidth, you have two approaches:

Put one 6502 on phase-1 clock, and the other on phase-2. This way, each CPU gains access to the shared bus on opposite clock levels. Advantage = This is perhaps the simplest possible approach. Disadvantage = You're limited to only two masters.

More sophisticated ways exist involving creating two complete CPU cards, each considered a "bus master" on an otherwise CPU-agnostic backplane bus (e.g., NuBus, VME bus, STE, etc). These two cards work with local memory and local I/O for the most part, and as such, do not always hit the global I/O bus. When they do, however, RDY must be negated to halt the CPU long enough to allow the card to be granted access to the global bus. Advantage = you're allowed as many processor cards as you want (the I/O backplane becomes a kind of network link between them). Disadvantage = you'll need to become familiar with the operation of the bus, and how to manage bus mastership.

That is excellent info!

One thing though. Phase 1 is not just an inverted Phase 2, at least not according to the old MOS manuals... Or can we get away with a common Phase 2/inverted Phase 2?

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

multiprocessing discussed here (Don't stop at page 1 if there's more):
viewtopic.php?t=406
viewtopic.php?t=217
viewtopic.php?t=1362

The Commodore data sheets I have indicates phase 1 is just phase 2 inverted. At any rate, I do know that the CMOS parts are definitely inversions of each other.

The old Commodore and Apple chipsets (and, I believe, Atari too) used to use phase 1 for their video chip and DRAM refresh accesses. Also, older Commodore disk drive units used to have two 6502s in them, both running on opposite phases of each other.

I commented on phase 1, because I remember the pictures in the MOS manual. The on time for phase 1 was a little less than the off time for phase 2, or maybe I just bumped my head and I'm remembering erroneous info through the fog of time. I didn't have time to look it up. Anyway, I have added that bit clarified info to my memory banks.

Good reads, thanks for digging that info up Garth. If I ever start toying with it, as it's in the back of my mind with all this FPGA stuff, I'll know where to post theoretical ideas. That's a big IF though, right now. One thing is pretty clear: one definately has to have a clear task in mind in order to determine if the ram will be shared and if the eeprom/(O.S.) will be shared, etc. I do have my eye on some dualport RAM.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502