OwenS wrote:
1. load/store multiple of any arbitrary register combination
Yes, thats right. One can do "STM r0, {r0-r15}" if they want to and save every register. LDM is the same.
68000 -- check. movem.l d0-d7/a0-a6,-(a7) is a common occurrence in 68K listings.
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2. Address updates available for every memory instruction
Reusing STM from above, "STM r0!, {r1-r15}", will write the final address to r0 (I've forgotten the exact specifics here). Pretty much every memory op supports this
68000 check. Register pre-decrement and post-increment works in any effective address, including move-multiple, as indicated above.
However, base+offset will not cause a register to be updated (a la PowerPC). I can't see a use for such a thing, never having had a need to even use LEA.L before. (I have had to use LEA on x86 to overcome a register shortage, and the 3-operand add it provides was nice in a jiffy.)
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3. The stack is my territory, and mine alone
The processor will never touch the stack. I don't have to deal with processor built stack frames. This greatly simplifies some things
The 68000 has a hardware stack assigned to register A7. However, seven other address registers exist, all of which are capable of serving as user-supplied stacks.
The hardware imposes a stack frame only on the supervisor stack, which is the domain of the OS kernel alone. The CPU does push a return address on the A7-stack when invoking BSR or JSR, but otherwise, the stack is your domain as well. Except for leaf subroutines, though, not having to manually stack the PC is awfully convenient.
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5. Three operand instruction setWell, that one should be reasonably clear
![Wink ;)](./images/smilies/icon_wink.gif)
I've not noticed, personally. Working with the MIPS architecture, I found no difference in preference to MOV EAX,EBX; ADD EAX,ECX over ADD R2,R1,R0. To some extent, I prefer the 2-operand forms, because then I don't have to keep specifying the same register over and over again in subsequent instructions.
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6. No mode flags (or those which exist are implicit)
For example, while there are both the ARM and Thumb instruction sets, they're designated by the least significant bit of the branch target address.
The BX/BLX instructions automatically move this bit into the current program status register (CPSR)
Contradictory -- clearly there is a mode flag here. Perhaps you meant that no instructions to manually set or clear this flag exists? If so, I can concede that's nice, when compared against the 65816. But the 68000 also lacks such instructions, too.
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7. PC is in the register file
Yes, you can do "MOV pc, lr" (this is the traditional way to return), and can use the ALU operations for relative branches.
Unfortunately, this consumes two CPU registers (the PC and the link register) which you cannot use for anything else. Also, putting the PC in the register file itself makes it difficult to optimize the micro-architecture for very high performance (by which, I mean, something comparing to a POWER-architecture RISC). I won't say it's impossible, but I will say it'll take transistors to pull it off.