I discuss invalid address bus on 6502. If absolute X/Y indexed cross page boundary, then extra one cycle is taken to correct invalid high operand of address bus.
65816 is identical to 6502 if in emulation mode because it is back compatibility. 65816’s datasheet dated back on Marcy 1, 2000 claims that invalid address bus should never happen if emulation mode is turned off to be 16 bit native. I believe that datasheet is not accurate.
I did test Apple II gs in my own. I determined that both emulation mode and 16-bit native do show invalid address bus.
Please let me know when you find out. Thanks…

For example, Data Bank = 15, AA = 400A, X = DFFF
Cycle 1 à Address Bus: 02A004, Data Bus: BD
Cycle 2 à Address Bus: 02A005, Data Bus: 0A
Cycle 3 à Address Bus: 02A006, Data Bus: 40
FF is added to 0A = 09. Carry is set for high operand
Cycle 4 à Address Bus: 154009, Data Bus: Invalid
C + DF is added to 40 = 20. Carry is set for bank operand
C + 15 = 16
Cycle 5 à Address Bus: 162009, Data Bus: Low Data
Cycle 6 à Address Bus: 16200A, Data Bus: High Data

The VPA and VDA signals tell you when the memory accesses are valid - if you need to avoid stray accesses then you'd use those signals to qualify your address decoding.

I had assumed that the memory accesses are not defined when both VPA and VDA are low, but the latest datasheet does tabulate some descriptions of what happens in these 'Internal Operation' cycles. That's interesting, but I wouldn't want to rely on that behaviour.

Cheers
Ed

I have 65816's datasheet dated back on March 1, 2000. It does list address bus and data bus information each one cycle. Unfortunately, WDC removed it from the datasheet dated back two years ago. Do you have idea why they do it?

Each absolute address instruction is able to control I/O at one time. For example, LDA $C050 / $C051 are graphic / text softswitches. I can tell LDA instruction to turn on / off at two times (each instruction with 5 cycles) because during fourth cycle, it responds to I/O for first time with invalid address bus before during fifth cycle, it responds to different I/O second time with valid address bus. (Very interesting)...

Can you please provide me the information? I would like to find new version of 65816's datasheet so I can see list of address bus and data bus each cycle. Thanks...[/quote]

You should check the News section of this site, where it mentions where the latest datasheets can be found.

The Home page is worth a visit too: there are more places on this site than it seems from a look at the links in the header.