I am interested to discuss NMOS 6502 MPU chip. I feel that this topic is appropriate in the "General Discussions" instead of "Emulation and Simulation" because I focus to study NMOS 6502 MPU chip. I have decided to write 6502 Simulator using C++ Compiler. This 6502 Simulator is designed to behave like NMOS 6502 MPU chip in software.

This allows you to use Phase 0 Input (Renamed Phase 2 Input for CMOS 65C02) function. The Phase 0 Input function can simulate one clock cycle at this time. Then, you can get data from address bus and data bus directly each one clock cycle. It is a very interesting project.

If you are C++ programmer, you can put Phase_0_Input() function inside loop and you use printf() function to print address bus and data bus information each one clock cycle. It is useful to create a log how NMOS 6502 MPU chip is generated accurately in software. I am aware that it is slower performance, but it does to do with electronic manipulation.

I do have early 1970s NMOS 6502 manual and datasheet. It does contain clock cycle counting information on all 6502 instructions and hardware interrupts.

I have already implemented A0 through A15, D0 through D7, Sync, Set Overflow and Phase 0 Input from the pins of NMOS 6502 MPU chip. I am going to implement Ready, Phase 1 Output, Phase 2, RESET', IRQ' and NMI'. I think VCC and VSS are not necessary to be implemented. I don't know if Phase 1 Output and Phase 2 Output may be interested, but they are not used.

I ask you please provide me the information of Ready, RESET', NMI' and IRQ'. I do have information handy of 7 clock cycle hardware interrupt. I want to draw a picture. The picture shows clock cycle pattern of Phase 0 Input. I need to see how RESET', NMI', IRQ', and Ready respond by the following Phase 0 Input pattern.

Garth Wilson has provided information on his website to show how hardware interrupt shows clock cycle pattern.

You pull low on RESET' line during first clock cycle while it is possible for NMOS 6502 MPU chip to operate two more clock cycles. During third clock cycle and after third clock cycle, NMOS 6502 MPU chip is frozen while data on A0 through A15 and D0 through D7 are floating. After you pull high on RESET' line, it starts to initialize and restart NMOS 6502 MPU chip toward RESET Vector.

You pull low on IRQ' line during first clock cycle while one instruction is finished between first clock cycle and seventh clock cycle. Then, 7 clock cycle hardware interrupt sequence is complete and ISR starts. You can do multiple interrupts as you wish unless IRQ Disable Flag is set to zero during IRQ' line is low. The multiple interrupts will be aborted unless you pull high on IRQ' line.

I am not too sure how to implement NMI'. NMI' is very similar to IRQ'. It can do only one interrupt. If you want second interrupt, you need to pull high on NMI' line during two cycles and pull it low again.

Also, I am not sure how ti implement Ready for reading only.

I appreciate your help when you can do our best with your knowledge.


Bryan Parkoff